NEOX V Announced By Think Silicon As First RISC-V 3D GPU | Michael Larabel, Phoronix
Libre RISC-V community-driven effort to create a RISC-V graphics processor that basically amounts to a RISC-V core with vector extensions/improvements and running... Read more.
Yadro Takes Control Of Russian RISC-V Startup | Peter Clarke, eeNews Europe
Server and storage company Yadro has taken a controlling interest in Syntacore, a Russian developer of RISC-V processors. Yadro is part of Russia’s IKS Holding... Read more.
An open source SystemVerilog Test Suite | Antmicro
software, hardware, FPGA and ASIC design, for which we use, contribute to and produce a wide variety of open source tools. article: https://antmicro.com/blog/2019/11/systemverilog-test-suite/]]>... Read more.
Antmicro Exhibits At RISC-V Summit 2019: Renode, Fomu And Open Chip Design
RISC-V Summit 2019, the annual global conference for the disruptive open ISA that is paving the way for open digital design. The show will be hosted in the San Jose...... Read more.
SiFive Welcomes Ann Chin As SiFive IP Business Unit General Manager | staff, SiFive
SAN MATEO, Calif., Nov. 26, 2019 /PRNewswire/ — SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced... Read more.
Getting Started with Embedded Linux on RISC-V in QEMU | Jean-Luc Aufranc, CNX Software
HiFive Unleashed SBC ($999), or expensive FPGAs. Another solution is running Linux RISC-V via QEMU emulator, and I showed how to do this using BBL (Berkeley... Read more.
Bootlin’s Michael Opdenacker Gets You Started with Embedded Linux on RISC-V in Just 40 Minutes | Gareth Halfacree, AB Open
https://abopen.com/news/bootlins-michael-opdenacker-gets-you-started-with-embedded-linux-on-risc-v-in-just-40-minutes/]]>... Read more.
SparkFun Picks SiFive's FE310 to Power RISC-V-Based RED-V Thing Plus, RED-V RedBoard Dev Boards | Gareth Halfacree, Hackster.io
SparkFun has officially launched the RED-V Thing Plus and RED-V RedBoard, a pair of Feather-compatible Thing Plus-footprint and Arduino Uno-format development boards... Read more.
Imperas delivers highest quality RISC-V RV32I compliance test suites to implementers and adopters of RISC-V
Imperas developed compliance tests quantified by open source collaboration of verification coverage tools developed by Google Cloud Oxford, United Kingdom, November... Read more.
RISC-V Community News Collection: November 22, 2019
Andes Core and Secure-IC Strategic Alliance By Andes Technology, EET Taiwan Nov. 20, 2019 Coverage First European Pre-Exascale Supercomputers Forgo Homegrown CPUs... Read more.