Fraunhofer IMS: Trusted Embedded AI With RISC-V | Richard Oed, Elektronik Praxis
https://www.elektronikpraxis.vogel.de/fraunhofer-ims-vertrauenswuerdige-eingebettete-ki-mit-risc-v-a-874220/]]>... Read more.
Real-Time System Verification Tool Now Available For RISC-V Embedded Systems | Aimee Kalnoskas, Microcontroller Tips
SystemView reveals the true runtime behavior of an application by utilizing its real-time recording and visualization capabilities. It uses J-Link and Segger’s... Read more.
SEGGER SystemView for RISC-V Now Available | Segger
J-Link and SEGGER’s Real Time Transfer (RTT) technology for continuous real-time recording and live analysis. article: https://www.segger.com/news/segger-systemview-for-risc-v-now-available/]]>... Read more.
QuickLogic Teams with SiFive to Make eFPGA Technology Available via DesignShare Portfolio | QuickLogic
SAN JOSE, Calif., Oct. 16, 2019 /PRNewswire/ — QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded... Read more.
CHIPS Alliance Growth Continues With New Members And Design Workshop This November | PR Newswire
SAN FRANCISCO, Oct. 15, 2019 /PRNewswire/ — CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems,... Read more.
Intel And AMD’s Biggest Cloud Threat May Be An Open X86 Instruction Set | Paul Teich, Forbes
Well over 90% of cloud Infrastructure-as-a-Service (IaaS) instance types are based on Intel Xeon processors. Will AMD EPYC processors take significant cloud market... Read more.
Samsung To Fabricate RISC-V Chip With 14LPP In Partnership With SemiFive | Ramish Zafar, Wccftech
single report from China claimed that Samsung will make a big change on its next Exynos processor, tentatively dubbed as the Exynos 9830. The report claimed that... Read more.
Samsung Supports The RISC-V Instruction Set Architecture: The First OEM chip | cnBeta
按照SemiFive负责人Cho Myung-hyun透露的消息，芯片采用的是三星14nm LPP工艺。 目前，三星晶圆工厂的主要对手台积电已经导入RISC-V代工业务。两强加入将丰富RISC-V的生态，同时发展更多无晶圆纯设计公司客户。... Read more.
SiFive Adds RISC-V Micro-Instruction Cache For Slow Memories | Steve Bush, Electronics Weekly
SiFive has added a ‘micro instruction cache’ option to its Risc-V e2 core – the smallest of its Risc-V intellectual property offerings. article: https://www.electronicsweekly.com/news/design/eda-and-ip/sifive-adds-risc-v-micro-instruction-cache-slow-memories-2019-10/... Read more.
RISC-V: Fraunhofer IMS Introduces Microcontroller Core | All-Electronics.de
https://www.all-electronics.de/risc-v-fraunhofer-ims-stellt-mikrocontroller-kern-vor/]]>... Read more.