Libre RISC-V Hybrid CPU/GPU Looking For Cash | Nick Farrell, Fudzilla
The open source Libre RISC-V hybrid CPU/GPU project is applying for eight additional grants from the NLNet Foundation. For those not in the know, the NLNet Foundation... Read more.
SiFive Announces New DesignShare IP Partnerships | SiFive
SAN MATEO, Calif., Sept. 30, 2019 /PRNewswire/ — SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, announced today... Read more.
Renode 1.8 Release With Multi-Core GDB Support And New RISC-V Platforms | AntMicro
newest release of Renode, Antmicro’s open source multi-node simulation framework, adds new exciting pieces to your toolbox, along with support for even more RISC-V... Read more.
Andes and Dover Microsystems Partner to Deliver Professional Network Security Solution for RISC-V | Andes Technology
HSINCHU, TAIWAN , Sept. 25, 2019 – Andes Technology Corporation (TWSE: 6533), a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit... Read more.
Open ISAs Gaining Traction | Semiconductor Engineering
https://semiengineering.com/open-isas-gaining-traction/]]>... Read more.
The Growing Impact Of Portable Stimulus | Semiconductor Engineering
It has been a year since Accellera’s Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has... Read more.
SiFive Announces Key Enablement Of Trace And Debug | SiFive
SiFive, Inc., has announced the general availability of the latest update to SiFive Core IP and SiFive Core Designer in the Q3 2019 quarterly update. This release... Read more.
Andes Technology Announces Coming Up The North America Annual RISC-V CON 2019 Santa Clara | Andes Technology (Press Release)
Santa Clara, US – September 24, 2019 – The RISC-V CON 2019 held in Santa Clara on October 15 will feature the first independent analysis of the commercial... Read more.
Intensivate Uses SiFive's RISC-V To Develop Accelerator | Neil Tyler, New Electronics
SiFive, the provider of commercial RISC-V processor IP and silicon solutions, has announced that Intensivate is implementing SiFive Tilelink and cache technologies... Read more.