Phoronix Article: The State Of RISC-V For Debian 10 "Buster"
https://www.phoronix.com/scan.php?page=news_item&px=Debian-10-Buster-RISC-V-State]]>... Read more.
EE Times Article: RISC-V Moving Beyond Academia, New Group Offers Hardened SoCs
Google, Huawei, NXP, Samsung and STMicroelectronics, listened to a ‘state of the union’ on the architecture, software, tools, debug, verification, and security,... Read more.
CNX Software Article: Perf-V Is Another FPGA Based RISC-V Development Board
SiFive’s HiFive1 or Kendryte KD233 board. But beauty of RISC-V is that you can customize the instructions set, and if that’s your goal, an FPGA board provides... Read more.
Embedded Computing Design Article: X-FAB, Efabless Release First Silicon of “Raven” RISC-V SoC
http://bit.ly/2Rhkqop. ]]>... Read more.
EENews Europe Article: X-FAB Silicon Foundries Tapes-Out Open-Source RISC-V MCU
Together with crowd-sourcing IC platform partner Efabless Corporation, X-FAB Silicon Foundries has announced the first-silicon availability of the Efabless RISC-V... Read more.
Semiconductor Engineering Article: Week In Review: Design, Low Power
Andes Technology debuted its RISC-V FreeStart program, which makes the company’s N22 RISC-V CPU IP core available to download with no license fee; a royalty... Read more.
Leiphone Article: Berkeley Hands In Tsinghua To Set Up RIOS Laboratory, RISC-V Is Expected To Upgrade To The Most Advanced Level?
Tsinghua University. Professor David Patterson is the first expert to propose the “Reduced Instruction Set” (RISC) system. He is currently an honorary... Read more.
Sina Article: Qualcomm Invests Heavily In RISC-V Companies
Qualcomm announced yesterday that it invested $65.4 million in SiFive, a leading provider of IP and silicon solutions for commercial RISC-V processors. In addition... Read more.