Elektronik Article: RISC V Processor Cores Or Compliance
OneSpin tool suite for RISC-V Integrity Verification. The app provides the growing RISC-V community with a way to verify processor cores to ensure that no errors... Read more.
Semiconductor Engineering Article: Week In Review: Design, Low Power
OneSpin Solutions unveiled a formal RISC-V Verification App. The app is intended to exhaustively verify that RISC-V cores are developed and integrated with zero... Read more.
Data Center Knowledge Article: Companies Pushing Open Source RISC-V Silicon Out To The Edge
SiFive, a Silicon Valley startup built around the open silicon design, quickly sold out on a limited run of a single-board computer for RISC-V developers, HiFive... Read more.
Hackaday Article: New Part Day: A 64-Bit RISC-V CPU In Raspberry Pi Hat Form
Raspberry Pi Hat. The Grove AI Hat for Edge Computing is built around the Sipeed MAix M1 AI Module with a Kendryte K210 processor. This is a dual-core 64-bit RISC-V...... Read more.
Hex Five Adds MultiZone™ Security To The AdaCore Software Ecosystem
Hex Five Security Inc., creator of MultiZone™, the first trusted execution environment for RISC-V, today joined AdaCore’s Partner Program to enable the secure... Read more.
Elektroniktidningen Article: Premiere For IAR's RISC-V Compiler
IAR – a world-leading name in compilers for embedded processors – announces that its first C-compiler for RISC-V is ready for use. IAR is such an important... Read more.
Root.CZ Article: SiFive RISC-V Chips Can Be Paired With PowerVR GPUs
SiFive open and free RISC-V chips from SiFive can now pair with Imagination Technologies’ PowerVR GPU cores . While RISC-V is an open-source CPU architecture,... Read more.
ESM China Article: The European And American Open Source Community Complains That China Contributes Less, And The Head Said That This Is A Prejudice
https://www.esmchina.com/news/5210.html. Please note that the original article is in Chinese.]]>... Read more.
Electronics Weekly Article: Toolchain Supports RISC-V Cores
IAR Systems, has recognised the increased adoption of RISC-V-based designs, with the introduction of a C/C++ compiler and debugger toolchain to support RISC-V cores.... Read more.