SemiInsights Article: What Do You Think About RISC-V?
http://www.semiinsights.com/s/bdt/15/36922.shtml. Please note that the original article is in Chinese.]]>... Read more.
EET China Article: SoC Chip Design Focuses On The "Invisible Champion" Of Security IP
SoC provide internal analysis and detection technology include: UltraSoC, for its system-on-chip design process; Moortec, for its in-chip monitoring subsystem... Read more.
EET Taiwan Article: Open Source RISC-V Is Becoming The Future Of Hardware Design
https://www.eettaiwan.com/news/article/20190517NT31-interview-with-Chair-of-the-RISC-V-Foundation-China. Please note that the original article is in Chinese.]]>... Read more.
lowRISC Expands And Appoints New Members To The Board Of Directors From Google And ETH Zurich
lowRISC is a not-for-profit, community-driven organisation working to provide a high quality, security-enabling, open SoC base for derivative designs. The organisation... Read more.
Elektronik Praxis Article: Rigid RISC-V CPU: New Chip Stops Attacks Before They Start
A novel RISC-V-based processor architecture is designed to proactively protect against any threats. At 20 Hz, it randomly changes its own code and processed data. Previous... Read more.
Google Blog Post: Google Fosters The Open Source Hardware Community
Google and our customer’s success. We look forward to supporting the new domain of open source silicon to similarly benefit all participants. Working through its... Read more.
Bit-Tech Article: Google Extends lowRISC FOSSi Partnership
Google has announced it is increasing its presence in the world of free and open source silicon (FOSSi), extending its partnership with the lowRISC project. Unlike... Read more.
PULP Platform Partners With GreenWaves, Bitcraze For RISC-V AI Drone Controller
ETH Zurich, Greenwaves Technologies, and Bitcraze to develop a PULP-powered and wireless artificial intelligence module for drone use: the AI Deck. Based on the... Read more.
All Electronics Article: Embedded Design: What Innovations RISC-V Leads To
More than 135 companies have already successfully implemented the ISA for their respective projects. The number of members continues to grow as more and more providers... Read more.
An Introduction To The RISC-V-Based SweRV Core
This article by Zvonimir Bandić of Western Digital, introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up... Read more.