Crowd Supply Article: HiFive1 Rev B
SiFive’s E31 CPU core complex, a high-performance, 32-bit RV32IMAC core with a 16 KB L1 instruction cache, a 16 KB data SRAM scratchpad and hardware multiply/divide.... Read more.
CKB-VM As A RISC-V Instruction Set: Inspiration, Design, And Benefits
Nervos CKB-Virtual Machine (CKB-VM), a RISC-V instruction set based VM for executing smart contracts and written in Rust. We covered what the program does and why... Read more.
FierceWireless Article: Open Source Silicon Project Innovates Chips In Communications Networks
Esperanto, Google, SiFive and Western Digital. The CHIPS Alliance is committed to both open source hardware and continued momentum behind the free and open RISC-V... Read more.
EET China Article: RISC-V Brought To China, Not A High-Rise Rendering
https://www.eet-china.com/news/6434.html. Please note that the original article is in Chinese.]]>... Read more.
Silicon Republic Article: All Aboard The Compute Express: Intel Forges New Cloud Chip Pact
Google and Microsoft. The new processors, which are due to come on stream in 2021, will enable a new epoch in chip-to-cloud architecture. Interestingly, the move... Read more.
EE Times Article: Intel, RISC-V Rally Rival Groups
Alibaba, Cisco, Dell EMC, Facebook, Google, HPE, Huawei, and Microsoft. Separately, a handful of RISC-V proponents launched the CHIPS Alliance, a project of the... Read more.
Linux Foundation To Host CHIPS Alliance Project To Propel Industry Innovation Through Open Source Chip And SoC Design
Esperanto Technologies, Google, SiFive and Western Digital, all committed to both open source hardware and continued momentum behind the free and open RISC-V architecture.... Read more.
Electronics Weekly Article: One I Missed: Ultra-Low-Power Multi-Core RISC-V At ETH Zurich
ETH Zurich and the Energy-Efficient Embedded Systems (EEES) group of University of Bologna – towards an open, scalable hardware and software research platform... Read more.
Andes Technology Announces RISC-V Single-Core And Multicore Processors With DSP Instruction Set
Andes Technology today, Andes proudly announces the debut of its 32-bit A25MP and 64-bit AX25MP RISC-V multicore processors. The A25MP and AX25MP are the first commercial... Read more.
VentureBeat Article: Node.js And JS Foundations Are Merging To Form OpenJS
Google, Western Digital, SiFive, and Esperanto are backing the CHIPS Alliance and are committed to both open source hardware and momentum behind the RISC-V architecture.... Read more.