Google experiments with RISC-V | Nick Farrell, Fudzilla
SiFive RISC-V chips are being used by Google to run some of its AI workloads and tested in Google datacentres. SiFive’s Intelligence X280 is a multi-core... Read more.
The Automotive Space Gears Up to Take on RISC-V | Murray Slovick, Electronic Design
SiFive is creating a lineup of compute IP for MCUs, MPUs, and soon, SoCs, as well as vector-processing solutions tailored for automotive applications. The first... Read more.
Customising PolarFire® SoC FPGA for International Space Station Mission | Microchip Technology
Our Mi-V Ecosystem partner Emdalo Technologies Ltd. (Emdalo) has successfully customised PolarFire® SoC FPGA Linux® and associated boot flow for Skycorp Inc.’s... Read more.
ST to make European octacore RISC-V space chip with selectable cores | Nick Flaherty, EE News Europe
Space system designer CAES has built the first eight core fault tolerant chip that is selectable between different architectures, including RISC-V. The radiation... Read more.
Arm vs RISC-V? Which One Is The Most Efficient? | Gary Explains
Arm has been making power efficient processors for decades. RISC-V is relativity new and many parts of its specifications aren't even ratified, but that hasn't stopped... Read more.
Native RISC-V ROS chip targets robotics | Nick Flaherty, EE News Europe
Two European companies are developing a microcontroller chip using the open source RISC-V instruction set that is optimised to run the latest Robot Operating System... Read more.
SiFive RISC-V cores picked for Google AI compute nodes | Dan Robinson, The Register
Cor, that’s a shot in the arm for this upstart CPU ISA RISC-V chip biz SiFive says its processors are being used to manage AI workloads to some degree in...... Read more.
Google deploys SiFive’s Intelligence X280 processor for AI workloads | Sebastian Moss, Data Center Dynamics
Google is using the RISC-V-based SiFive Intelligence X280 processor in combination with the Google TPU, as part of its portfolio of AI chips. Fabless chip designer... Read more.
Codasip joins OpenHW to push RISC-V verification | Nick Flaherty, EE News Europe
German RISC-V core designer Codasip has joined the OpenHW group to push for advances in the verification of RISC-V cores. Codasip has highlighted issues with verification... Read more.
ARM IS THE NEW RISC/UNIX, RISC-V IS THE NEW ARM | Timothy Prickett Morgan, The Next Platform
When computer architectures change in the datacenter, the attack always comes from the bottom. And after more than a decade of sustained struggle, Arm Ltd and its... Read more.