In the Media

The previous article was a ‘look back’ at the computation paradigm and the context in which RISC-V has emerged as a new player. In this article, we ‘look sideways’ and in the…

Imperas reference models for Andes expanded with Andes Custom Extension™ support and design flow integration for leading EDA environments, plus new AndesCore® N25F-SE core for functional safety applications. Imperas Software…

DFRobot UniHiker is a STEM education platform with a 2.8-inch touchscreen display, a Rockchip RK3308 quad-core Cortex-A35 processor, a GD32V RISC-V microcontroller, WiFi and Bluetooth connectivity, as well as various…

CEVA, a licensor of wireless connectivity and smart sensing technologies, is to make its CEVA-BX1 and CEVA-BX2 Audio DSPs and audio front-end software stack available for commercial developers through the…

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The Sipeed M1s is a compact module integrating the Bouffalo Lab BL808 RISC-V SoC module along with a NPU. The device also provides WiFi/BL, 802.15.4 Zigbee connectivity and support for interfaces such…

The Codasip University Program joins Intel® Pathfinder For RISC-V Codasip, the leader in processor design automation and RISC-V processor IP, today announced it is collaborating with Intel® to enable undergraduate…

Oxford, United Kingdom – December 5th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Simon Davidmann has been elected as Chair of the OpenHW Verification Task Group…