In the Media

SiFive RISC-V chips are being used by Google to run some of its AI workloads and tested in Google datacentres. SiFive's Intelligence X280 is a multi-core RISC-V design with vector extensions.…

SiFive is creating a lineup of compute IP for MCUs, MPUs, and soon, SoCs, as well as vector-processing solutions tailored for automotive applications. The first automotive family cores will become…

Space system designer CAES has built the first eight core fault tolerant chip that is selectable between different architectures, including RISC-V. The radiation hardened GR765 System-on-Chip (SoC) is the first user selectable…

Arm has been making power efficient processors for decades. RISC-V is relativity new and many parts of its specifications aren't even ratified, but that hasn't stopped chip designers making RISC-V…

Two European companies are developing a microcontroller chip using the open source RISC-V instruction set that is optimised to run the latest Robot Operating System (ROS2). The roscore-v project aims…

Cor, that's a shot in the arm for this upstart CPU ISA RISC-V chip biz SiFive says its processors are being used to manage AI workloads to some degree in…

Google is using the RISC-V-based SiFive Intelligence X280 processor in combination with the Google TPU, as part of its portfolio of AI chips. Fabless chip designer SiFive said that it…

German RISC-V core designer Codasip has joined the OpenHW group to push for advances in the verification of RISC-V cores. Codasip has highlighted issues with verification of cores designed with…

When computer architectures change in the datacenter, the attack always comes from the bottom. And after more than a decade of sustained struggle, Arm Ltd and its platoons of licensees…

Oracle on Tuesday marked the release of Java 19 (JDK 19), the latest iteration of the popular general purpose programming language. In its evangelizing slide deck accompanying this release, Oracle…