In the Media

Watch the full event recording. 

This article is a primer into the basics of RISC-V. The open architecture philosophy is exposed, along with a technical description of the modular ISA, and some commercial RISC-V microprocessor…

Think Silicon®, a leader in ultra-low power graphics IP, will showcase the industry’s first RISC-V-based GPU – the NEOX™ G-Series & A-Series – at Embedded World 2022. The company will…

Codasip, the leader in customizable RISC-V processor IP, today announced it has appointed Mike Eftimakis as VP Strategy and  Ecosystem. Mike Eftimakis has an extensive background in the electronics industry…

Connue pour ses puces-systèmes ESP32 compatibles Wi-Fi, Bluetooth et Bluetooth Low Energy et très présente sur le marché des objets connectés, la société Espressif Systems étoffe son portefeuille avec l'ESP32-C5.…

RISC-V (pronounced Risk Five) is a relatively new computer technology that is being actively promoted as a competitor to ARM. A guide has been written and published to provide students…

Monte Cimone cluster combines 32 RISC-V cores. A group of researchers from the Università di Bologna and Cineca has explored an experimental eight-node 32-core RISC-V supercomputer cluster. The demonstration showed…

Microchip continues the push for RISC-V hardware by reaching milestones with its PolarFire system-on-a-chip (SoC) field-programmable gate array (FPGA) and Mi-V ecosystem. One major trend in the field of computing…

Debugging RISC-V apps can be exhaustive and at times ineffective. However, a high-level-language debugger offers shortcuts to boost efficiency and gives you complete control over the code and all instructions.…

Lauterbach’s debug tool now supports the EMSA5-FS functional safety processor core developed using the open RISC-V instruction set architecture. EMSA5-FS was developed by Fraunhofer Institute for Photonic Microsystems (IPMS) as…