Well known people in the industry such as Dave Jaggar, Jim B. Keller and Dave Ditzel give RISC-V the thumbs up. The more I write about RISC-V the more realize…
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Imperas RISC-V Reference Model, Test suites and Verification IP for advanced ‘lock-step-compare’ Processor Verification including Asynchronous events and Coverage Analysis. Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced…
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Ashling has announced that Ashling’s RiscFree Toolchain will provide support for Intel FPGAs including Intel’s Nios V Processor later this year. “Intel is pleased to work with Ashling to enable…
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2022 marks the 20th year of HPCwire‘s People to Watch Program, which recognizes HPC professionals who play leading roles in driving innovation within their particular fields, making significant contributions to society…
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Ashling and MIPS announced today that Ashling’s RiscFree™ Toolchain has been extended to support MIPS RISC-V ISA based IP cores. RiscFree™ is Ashling’s Integrated Development Environment (IDE) including a compiler and debugger for RISC-V…
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Fans of this newsletter know I’m a major chip nerd. I started my tech career as a semiconductor reporter, and for the last seven or eight years I’ve been closely…
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SEGGER’s Embedded Studio for RISC-V, Version 6, now uses real-time memory management which improves efficiency and response time when allocating and freeing up memory, satisfying requirements for hard real-time in applications…
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RISC-V Gets Sv57-Based Virtual Memory, Other Improvements For Linux 5.18 | Michael Larabel, Phoronix
The RISC-V CPU architecture updates have landed for the in-development Linux 5.18 kernel. Notable with the RISC-V additions for Linux 5.18 is sv57 support for 5-level page tables. It was just with the…
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Hundreds of variations of open-source CPUs written in an HDL seem to float around the internet these days (and that’s a great thing). Many are RISC-V, an open-source instruction set…
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Dongshan Nezha STU is a development kit comprised of an Allwinner D1 RISC-V system-on-module (SoM) and a carrier board with three 40-pin headers to access I/Os from the RISC-V processor.…
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