Is RISC-V the future? This is a question that we often get asked, and let’s assume that we mean ‘is the RISC-V going to be the dominant ISA in the…
Read More
Leading the RISC-V uprising drives SiFive, home of the inventors of RISC-V, to continue to push forward with developing our product families and technologies. Earlier this year, we debuted the…
Read More
DRAC is a research project with the aim to produce RISC-V processors and different accelerators trying to achieve the maximum possible performance while minimizing power consumption. To accomplish that, a…
Read More
RISC-V has attracted a great deal of interest across the computing industry for its open-source instruction set architecture and rapidly evolving ecosystem. There are reports that Russia plans to build…
Read More
Together with industrial partners, the University of California, Berkeley has developed the „Reduced Instruction Set Computer V“ (RISC-V) using an open instruction set architecture (ISA). The goal of the project…
Read More
René Rebe managed to patch the Linux kernel to support the RISC-V processor along with the AMD RX 6700 XT card in around 10 hours. The GPU is not exactly…
Read More
Since last Friday, five openSUSE Tumbleweed snapshots have been released. GNOME 40, btrfs, Mesa, Wireshark and several other package updates landed this week in the rolling release. The last snapshot…
Read More
When SiFive introduced its HiFive Unmatchd RISC-V desktop motherboard for developers last year, it was clear from the start that sooner or later an enthusiast would attempt to try using its U7 SoC…
Read More
Read the full article and watch the interview. "One of the popular types of entries to MPW1 & 2 have been FPGAs. I have previously spoken with Arya Reais-Parsi about…
Read More
What is Zephyr RTOS? Why would I chose Zephyr over Linux? How is it open source? What is the Zephyr Project and how does it relate to the RTOS? These…
Read More