Aldec announced a “TySOM-M-MPFS250” SBC that runs Linux on Microchip’s RISC-V based, FPGA equipped PolarFire SoC and offers 2x GbE, 2x FMC, 2x micro-USB, PCIe x4, CAN, HDMI, and PMOD.…
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The 1st TinyML meetup was held virtually as an open panel discussion with the keynote speakers. The group discussed the landscape and potential of today’s ultra-low-power applications, recent advances and…
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The Amp Hour Podcast welcomes back Antmicro's Michael Gielda who was on episode 519 talking about simulating embedded hardware using Renode He returned to talk about other projects that Antmicro…
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Almost 700 people registered for the first-ever Zephyr Developer Summit, which took place virtually on June 8-10, to learn more about the RTOS. We had 3 tracks, 5 mini-conferences, 28…
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Watch a video tutorial showing the steps involved in creating a 32-bit RISC-V CPU. See the full video here.
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Watch Filip Szkandera talk about a homemade 32-bit RISC-V CPU. It runs at 500 kHz, has 512 kB RAM & program memory. VGA output is black and white picture with…
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The Institute of Computing Technology at the Chinese Academy of Sciences (ICT CAS) has showcased progress on a fully open-source processor, designed around the RISC-V architecture, which it hopes will…
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Profiler is a part of our GAP SDK and used with GVSOC, our Full System SoC Simulator. Profiler gives you a visual view of what is happening inside the chip…
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SiFive Performance P550 was supposed to be the most powerful RISC-V core to date, capable of outperforming Arm’s Cortex-A75 core in raw performance, but especially in terms of efficiency, with three…
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Open source software is omnipresent in the server and cloud world, with open source operating systems, container runtimes, as well as frameworks for device management, monitoring and data pipelining, workload execution etc.…
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