In the Media

InCore and Tessolve announce the availability of our open source RISC-V Core Verification tool - RiVer Core. RiVer Core is a python based extensible and scalable framework aimed at providing…

See Mitchell Horne discuss the latest developments of FreeBSD on RISC-V. Watch the full video here. 

RISC-V, the open-source instruction set architecture, is making inroads against industry giants, with the support of the RISC-V Foundation. Recently, RISC-V has been stirring up the industry with talk about competing with…

There’s an understandably high level of interest in RISC-V processors among our community, but while we’ve devoured the various microcontroller offerings containing the open-source core it’s fair to say we’re…

What brought gaming PCs to their knees back in 1996 can now run on a microcontroller — albeit a surprisingly powerful one. Mathias Claussen has put together a guide to…

The demand for deploying machine learning models, especially state-of-the-art deep neural networks on edge devices is rapidly growing. Edge AI allows to run inference locally, without the need for a…

Intel and SiFive made a pair of announcements yesterday that underscore how serious the chip giant is about ramping its own foundry services. First, Intel has announced it has reorganized…

Sub-$13 system comes with RT-Thread Studio IDE support, audio capabilities, and even an infrared receiver. Chinese electronics specialist Bluetrum has announced the launch of a RISC-V development board built around…

Arm is a RISC Instruction Set Architecture (ISA) and simultaneously a company that designs RISC CPU cores. RISC-V is also a RISC ISA, but not also a design company. Are…

In this video interview with HPCwire’s Managing Editor Tiffany Trader, Jean-Marc Denis, European Processor Initiative (EPI) chair of the board and head of strategy at Atos, details ongoing EPI activities…