MIPS released its P8700 CPU based on the RISC-V computing architecture to target driver assistance and autonomous vehicle applications. The San Jose, California-based company, which focuses on developing efficient and configurable…
Formal For All! “Do I need a PhD to use formal verification?” “Can formal methods really scale?” “Is it too difficult to write formal properties that actually prove something?” “If…
What you’ll learn: The state of RISC-V, including new RISC-V announcements. A look at some good video presentations at the 2024 RISC-V Summit. RISC-V trends in 2025. I didn't make…
San Jose, CA — Oct. 22, 2024 — Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, are proud to announce…
RISC-V is an industry standard instruction set architecture (ISA) born in UC Berkeley. RISC-V is the fifth iteration in the lineage of historic RISC processors. The core value of the…
Last week’s RISC-V Summit in Santa Clara, Calif., had an air of confidence that we have not seen at previous summits. There was much for this tight-knit community to shout…
In this roundup, we discuss several announcements from last week's summit pushing RISC-V adoption and processing power. Four companies, including Andes Technology, RISC-V International, Arteris, and Codasip, made significant announcements…
San Jose, CA — Oct 22, 2024 — DeepComputing, a pioneer in RISC-V innovation, today announced a strategic partnership with Andes Technology Corporation, a leading provider of high-efficiency, low-power 32/64-bit RISC-V processor cores. Together,…
It looks like the upcoming Linux 6.13 cycle will be adding RISC-V support for user-space pointer masking and tagged address ABI. RISC-V pointer masking can be used for implementing memory tagging akin…
Leading Japanese automotive supplier Denso is expanding its semiconductor business through a development license agreement for a Neural Processing Unit (NPU) AI core from Quadric in the US, adding its…