Microchip is qualifying an eight core fault tolerant RISC-V processor for AI in space applications. The radiation tolerant PIC64-HSPC octal core 1.2GHz switch provides 26K DMIPS and is built on…
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Microchip has launched its first 64bit microprocessor line, starting with a multicore RISC-V cluster for its PIC64GX family. The PIC64 GX1000 uses the existing RISC-V four core cluster with a…
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Munich, Germany — During the recent RISC-V Summit Europe, EE Times had the opportunity to talk to a leading RISC-V researcher Frank Kagan Gürkaynak, a senior scientist at ETH Zürich…
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European startup Vybium is developing am AI accelerator chip using the open RISC-V instruction set architecture to take on the Nvidia A100 GPU in the data centre. Vybium is a…
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In this course, our Founder and CEO, Mr. P R Sivakumar, explains the layered architecture of RISC-V open ISA and how we chip designers design various chips like simple embedded…
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At this year’s Design Automation Conference (DAC), I was told that the committee had received some 1,500 technical paper and presentation submissions, and a 34% increase in research paper submissions,…
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Milk-V , a developer of RISC-V-related hardware, has announced the Milk-V Jupiter, a Mini-ITX motherboard equipped with a RISC-V processor. Milk-V Jupiter | RISC-V PC for Everyone https://milkv.io/jupiter RISC-V is…
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This weekend we ended up working a lot on two RISC-V designs in a push to get the final PCBs out the door. First up is the CH32v203 QT Py.…
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Germany was buzzing this week. No, not because of the Euros. Munich also hosted the 2024 edition of the RISC-V Summit Europe, and Codethink was in town! RISC-V Summit Europe…
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RAID RISC-V NAS built using a Banana Pi BPI-F3 single board computer and a JMB582 PCIe to SATA adapter. Watch the video.
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