This week, the 2024 edition of RISC-V Summit Europe took place in lovely Munich, Germany. Those of us who attended last year’s edition in Barcelona might not have expected the…
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At every point in the design process, RISC-V developers can make use of the advancements presented at RISC-V Summit Europe. It’s been a big week for open-source processors as the…
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Munich, Germany. SiFive, Inc. announced an innovative design of its SiFive Essential product family at the RISC-V Summit Europe 2024. With over a decade of development, the Essential IP has demonstrated…
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Axiomise’s Nicky Khodadad and Ashish Darbari discuss simulation and the need for formal verification and RISC-V, including why simulation-based verification is inadequate to find all the bugs in a design…
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SiFive is seeing growing adoption, with more than two billion SiFive RISC-V-based chips already in the market. SiFive, Inc. the gold standard for RISC-V computing, unveiled a major upgrade of…
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RISC-V is an emerging choice for semiconductor companies to create highly differentiated products for a wide range of end applications. Both established players and start-up companies are investing heavily and…
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Semidynamics Tensor Unit efficiency data for its “All-In-One” AI IP, which uses a LlaMA-2 7B-parameter Large Language Model (LLM), has been made public. Roger Espasa, Semidynamics’ CEO, explained, “The traditional…
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Combining IP from two RISC-V leaders with an independently developed NPU brings advanced AI acceleration and rich user interfaces to ESWIN Computing’s EIC77 Series SoCs. June 25, 2024 -- Today,…
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SiFive announced the 4th generation of RISC-V CPU cores for embedded applications at RISC-V Summit Europe 2024 today. There are eight cores, three of which are 32bit while the other…
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Watch the first of our roundups from DAC 2024, taking place this week at the Moscone Center in San Francisco, where we talk about the EDA, tools and support for…
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