In the Media

Join us for the next Technology Update featuring informative, technical talks on open source hardware collaborative development. Hosted by Google in Sunnyvale, California, the event includes speakers from Google, Antmicro,…

RISC-V is an open-source instruction set architecture that can be used to develop custom processors. It's challenging not just Intel and AMD but Arm as well. Here are the top…

The ESD Alliance hosted an engrossing evening in the early days of RISC-V featuring two of its authors. At the time, RISC-V was a fledgling concept and it’s doubtful anyone…

October-17, 2023, Chennai, India and Limerick, Ireland. Fabless processor core IP provider InCore Semiconductors and embedded tools developer Ashling today announced support for the Azurite family of RISC-V processor cores…

CHANDLER, Ariz., October 25, 2023, RISC-V Summit — Designers who create systems for the complex Intelligent Edge need flexible, high-performance hardware and system-software combinations that easily handle demanding workloads while meeting…

RISC-V is inevitable - it became the mantra of RISC-V, and it's true. But before we see why that is, let’s step back and discuss what RISC-V is and why…

SemiDynamics in Spain has developed a RISC-V Tensor Unit for AI chip design based on its fully customisable 64bit cores. The RISC-V Tensor unit is integrated into the cache sub-system,…

Barcelona, Spain – 24 October, 2023. Semidynamics has just announced a RISC-V Tensor Unit that is designed for ultra-fast AI solutions and is based on its fully customisable 64-bit cores. State-of-the-art…

Introducing the highly flexible 700 family for unlimited innovation Munich, Germany, 17 October 2023 – Codasip, the leader in RISC-V Custom Compute, announced today a new highly configurable family of…

The security chip (at the middle of the bottom) is built in flip-chip technology on an auxiliary board and plugged into a standard socket on the main board. The main…