In the Media Archives

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Dec 12

Codasip Launches SecuRISC5 initiative

By Alicia Daleiden In the Media

Munich, Germany – December 12, 2022 – Codasip, the leader in processor design automation and RISC-V processor IP, today launched SecuRISC5, a Codasip initiative to provide its customers with safe…

Dec 12

Imperas releases new updates, test suites, and functional coverage library to support the rapid growth in RISC-V Verification

By RISC-V Community News In the Media

Oxford, United Kingdom – December 12th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates to ImperasDV to support the rapid growth in RISC-V verification…

Dec 08

Microchip Showcases RISC-V-Based FPGA and Space-Compute Solutions at RISC-V Summit

By Alicia Daleiden In the Media

CHANDLER, Ariz. – December 8, 2022 – Mid-range FPGAs and System-on-Chip (SoC) FPGAs have played a major role in moving computer workloads to the network edge. Microchip Technology (Nasdaq: MCHP) has helped fuel…

Dec 08

Imperas and Imagination Collaborate on Providing Virtual Platform Models for the Catapult RISC-V CPU Family

By RISC-V Community News In the Media

Oxford, United Kingdom – December 8th, 2022 – Imperas Software Ltd.,the leader in RISC-V simulation solutions, today announced that Imagination Technologies, a global technology leader in silicon IP (intellectual property), has approved the…

Dec 07

Codasip Launches Codasip Labs to Accelerate Advanced Technologies

By Alicia Daleiden In the Media

Munich, Germany – December 7, 2022 – Codasip, the leader in processor design automation and RISC-V processor IP, today announced the establishment of Codasip Labs as an innovation hub within the…

Dec 07

Andes Announces RISC-V Multicore 1024-Bit Vector Processor: AX45MPV

By RISC-V Community News In the Media

SAN JOSE, CA – December 7, 2022 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V…

Dec 07

Andes Technology Unveils The AndesCore™ D23, A Feature-Rich, Low-Power And Highly-Secured Entry-Level RISC-V Processor

By RISC-V Community News In the Media

SAN JOSE, CA - December 7, 2022 - Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V…

Dec 07

Join Andes At RISC-V Summit; Learn The Only ISO 26262 Fully-Compliant RISC-V CPU, The Latest Multicore 4-Way Out-Of-Order Processor & The Multicore 1024-Bit Vector Processor

By RISC-V Community News In the Media

Dec 07

Andes Technology And Parasoft Collaborate To Provide Seamless Software Testing Tools For Automotive Functional Safety Applications

By RISC-V Community News In the Media

SAN JOSE, CA - December 7, 2022 - Andes Technology, a leading supplier of high-performance, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, and Parasoft, a global…

Dec 07

MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors

By RISC-V Community News In the Media

Oxford, United Kingdom – December 7th, 2022 – Imperas Software Ltd.,the leader in RISC-V simulation solutions, announced today that MIPS, a leading developer of highly scalable RISC processor IP, has selected Imperas…

In the Media

Codasip Launches SecuRISC5 initiative

Imperas releases new updates, test suites, and functional coverage library to support the rapid growth in RISC-V Verification

Microchip Showcases RISC-V-Based FPGA and Space-Compute Solutions at RISC-V Summit

Imperas and Imagination Collaborate on Providing Virtual Platform Models for the Catapult RISC-V CPU Family

Codasip Launches Codasip Labs to Accelerate Advanced Technologies

Andes Announces RISC-V Multicore 1024-Bit Vector Processor: AX45MPV

Andes Technology Unveils The AndesCore™ D23, A Feature-Rich, Low-Power And Highly-Secured Entry-Level RISC-V Processor

Join Andes At RISC-V Summit; Learn The Only ISO 26262 Fully-Compliant RISC-V CPU, The Latest Multicore 4-Way Out-Of-Order Processor & The Multicore 1024-Bit Vector Processor

Andes Technology And Parasoft Collaborate To Provide Seamless Software Testing Tools For Automotive Functional Safety Applications

MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors

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About

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Join RISC-V International

Becoming a member of RISC-V International allows companies and individuals to actively influence the development of an open, royalty-free instruction set architecture, driving innovation in custom processor designs.