RISC-V is growing rapidly in adoption and attention and leading up to the RISC-V Summit, taking place in Santa Clara November 7 and 8, Codasip has introduced its 700 family of RISC-V baseline processors, designed for custom embedded solutions of all types, and it’s also announced the industry’s first commercial implementation of the Capability Hardware Enhanced RISC Instructions (CHERI) security technology for RISC-V.
