Next week, Nuremberg will once again host one of the longest-running and most technically comprehensive events in the global electronics calendar. Founded in 2003, Embedded World began as a highly specialised exhibition centred on microcontrollers. Today, it is a broad industry forum welcoming silicon vendors, IP providers, toolchain companies, industrial automation specialists, robotics developers, security experts – and increasingly, edge AI players.
From automotive safety in software-defined vehicles to fault-tolerant, space-bound robotics, the embedded market has grown, too. This new breed of embedded application requires not only performance but predictability, longevity and efficiency, while mission-critical use cases demand hardware certified to meet rigorous safety and security standards. While much of the embedded market once depended on commercial off-the-shelf (COTS) components, differentiation today lies in tailoring compute to exact workload, power and lifecycle requirements. Customization is no longer the cherry on top, it’s a competitive advantage – something we’ll be exploring directly in two panel sessions next week (details at the end of this post).
RISC-V was created as a clean, highly configurable instruction set architecture (ISA) to target deeply embedded environments that demand this level of customization. And while RISC-V has grown into Linux-capable application processors and HPC-class designs, embedded remains its most fertile proving ground.
To bring all of this to life, RISC-V International will be joined by Akeana, Andes Technology, DAMO / XuanTie, Nuclei Systems, Semidynamics, Siemens EDA, SiFive and Tenstorrent at the RISC-V Pavilion (Hall 5, 119). We’ve designed the space to offer visitors a one-stop-shop for you to explore the breadth of RISC-V deployment, from ultra-low-power MCU-class cores and safety-critical automotive IP to vector-enabled processors, AI accelerators and toolchains.
In preparation for this year’s show, I’ve been speaking with some of our members, co-exhibitors and panellists about what they’ll be bringing to Nuremberg and how it represents the state of the embedded ecosystem in 2026. Through these conversations, three themes stuck out to me:
1. Production Readiness Will Define RISC-V In 2026
The RISC-V powered Amazfit T-Rex 3 Pro smart watch. Image courtesy Amazfit
In its formative years, RISC-V conversations at Embedded World often centred on architectural promise and ecosystem trajectory. In 2026, the emphasis has shifted decisively towards compatibility, scalability and above all, production readiness.
Production readiness is no longer theoretical; it is visible in shipping products. Andes Technology (RISC-V Pavilion) will provide a clear illustration of this with the Amazfit Smart Watch T-Rex 3 Pro, powered by the AndesCore™ D25F. This is not a development board but a commercial smart watch product that has shipped over one million units globally, delivering extended battery life while supporting increasingly sophisticated GPS and bio-tracking functionality. It is a reminder that RISC-V cores are not confined to evaluation kits; they are embedded in devices that consumers depend on daily.
At the silicon IP level, Nuclei Systems (RISC-V Pavilion) reinforces the same message of scale and maturity. With more than 300 global licensees and billions of SoCs already deployed in Asia, the company is bringing RISC-V maturity at volume into Western automotive and industrial markets. Its portfolio spans from ultra-low-power MCU-class cores to higher-performance application-class designs, including ASIL-D compliant CPUs already licensed to major automotive customers.
Nuclei founder Bob Hu believes the real “revolution” is happening where safety, reliability and efficiency are non-negotiables. “Our goal for 2026 and beyond is simple: remove any barrier to RISC-V adoption,” he says. “We want to help innovators meet their toughest challenges – not just the technical ones, but the business ones too.”
If high-volume consumer deployment and scalable IP demonstrate production viability, the ultimate test lies in control within safety-critical vertical markets – namely automotive. This emphasis on production-grade deployment is echoed by established automotive semiconductor leaders such as Infineon (Hall 4A, 138), whose presence at Embedded World reflects the reality that RISC-V discussions are increasingly taking place around long-lifecycle, safety-qualified automotive programs.
And when it comes to safety-critical functions, few workloads are less forgiving than automotive braking. Visitors will find an automotive braking control system built on Quintauris’ RT-Europa reference platform on IAR Systems’ stand (Hall 4, 349), integrating Andes IP, the IAR functional safety toolchain for RISC-V, the IAR C-SPY debugger, and Vector MICROSAR Classic software.
“Embedded systems, particularly in automotive and industrial environments, demand determinism, efficiency, functional safety, and long lifecycle stability,” says Ozgur Ozkurt, CTO of Quintauris – a collaboration between leading semiconductor and automotive technology companies founded by Bosch, Infineon, NXP and STMicroelectronics. “At EW we’ll be showing a foundation for automotive real-time computing. This is about turning architectural openness into engineering confidence, aligning the ecosystem around production-grade RISC-V solutions.”
“RISC-V is no longer just about architectural freedom, it’s about production readiness”, affirms Jakob Ågren, Chief Product Officer at IAR. “We’re showing hard real-time automotive control with AUTOSAR Classic and functional safety tooling. That’s core embedded: deterministic behavior, safety compliance, and certification readiness. If RISC-V succeeds here, it succeeds everywhere.”
Beyond the braking demo, further Quintauris collaborations focus on industrialisation and validation. With embedded tools leader TASKING (Hall 4, 150), emphasis is on toolchain integration, validated software stacks and cross-vendor interoperability: practical ingredients for production viability. Meanwhile, Quintauris’ work with electromagnetic drive and gearing manufacturer WITTENSTEIN (Hall 4, 337) centres on structured validation, repeatable testing environments and certification-oriented assessment frameworks designed to accelerate safety-qualified deployment.
Across all of these examples, the vocabulary has shifted from exploratory to operational: design-in, certification, qualification, units shipped. All very positive signs that in 2026, aspiration has become execution.
2. Automotive Is The Benchmark For RISC-V In Embedded
Infineon Technologies is soon to launch a new family of automotive IP based on RISC-V
Automotive SoC architectures are in flux. As an open standard, RISC-V’s modularity and flexibility enable domain-specific processors, accelerators, chiplets and SoCs to be developed directly for the target application. However, the automotive market demands much more in terms of technical and ecosystem maturity. It requires validated safety frameworks, predictable toolchain behaviour, cross-vendor interoperability, long lifecycle guarantees and alignment across silicon, middleware and integration partners.
Infineon recently committed to adopting RISC-V for its next-generation automotive microcontroller families. At Embedded World, it will be demonstrating how microcontrollers, sensing technologies and power architectures underpin the shift toward zonal and software-defined vehicle platforms. Its presence reinforces that the automotive RISC-V conversation is not confined to emerging IP providers, but intersects directly with Tier-1 production programs operating at scale.
Embedded computing has long stood for tightly scoped workloads, bare-metal (or lightweight RTOS) execution and limited memory footprints. Systems that prioritise determinism over abstraction, running tightly written control loops that read sensors, drive actuators and manage timing. That foundation remains essential for so many of the tiny components that proliferate our world, yet when it comes to complex use cases like automotive, embedded systems increasingly sit beneath structured software layers such as AUTOSAR, safety-qualified toolchains and validated debugging environments. In this sense, embedded in automotive is climbing the software stack — not abandoning determinism, but integrating higher layers of functionality while preserving it. The braking control system you’ll see on IAR’s stand is as much about full-stack integration as it is about processor capability.
Of course, the more we move beyond base hardware towards software-rich systems, the greater the risk of fragmentation. By focusing on vendor-neutral reference architectures, validated implementations and cross-vendor interoperability, organizations like Quintauris are addressing this key challenge head-on. Embedded developers cannot afford ambiguity in safety-critical or long-lifecycle deployments. They need defined baselines, predictable integration paths and coordination across silicon, tooling and middleware providers.
The broader question of automotive readiness will be explored in a panel discussion at EW (details below). The panel will focus not only on whether RISC-V can meet functional requirements, but whether the ecosystem of silicon vendors, IP providers, software toolchains and Tier 1 suppliers has reached the level of coordination necessary for large-scale deployment. Automotive is not simply another vertical for embedded; it’s the arena in which architectural openness must prove itself under the most demanding conditions.
3. Edge AI Is Pulling Vector, SIMD And NPUs Into Embedded
The proliferation of edge AI capabilities throughout the embedded space is evidenced by companies like Semidynamics (RISC-V Pavilion), which will be demonstrating its Cervell NPU – comprising a uniquely unified scalar, vector, and tensor architecture – at Embedded World. By removing the need for discrete accelerators and the overhead of shuttling data between them, Semidynamics offers not only higher performance per watt but a more predictable, deployable AI stack; one capable of scaling from compact inference nodes through to more demanding LLM workloads. Complementing the hardware, the company will be showing off new inferencing tools designed to shorten the path from ONNX model to production deployment on Cervell.
SiFive (RISC-V Pavilion) will also be demonstrating an AI-centric IP combining scalar, vector and matrix compute in the form of its X160 processor, part of its second-generation Intelligence family, running AI workloads including TinyML. The company will showcase how RISC-V vector performance on the X160 compares favourably to incumbent embedded platforms, underlining the growing competitiveness of RISC-V in AI-enabled microcontroller-class deployments. Company executives will also be on hand to discuss SiFive’s broad automotive, embedded and IoT solutions designed to bring AI to the edge across a wide range of markets and applications.
Tenstorrent (RISC-V Pavilion), often associated with high-performance compute and AI acceleration, will extend this theme across embedded, real-time and high-performance classes at the show. Notably, it’ll be demonstrating the lightweight LLM TinyLlama running on its embedded IP, illustrating how even compact, power-conscious cores are now capable of supporting meaningful AI inference workloads.
Beyond SoCs for rugged smartwatches, Andes will be bringing its portfolio of MCU-class cores to Nuremberg, packed with SIMD/DSP extensions, vector-enabled multi-core processors, and automotive-grade safety enhancements.
“As AI moves from the cloud to the edge, the demand for high-performance, safety-critical compute has never been greater”, says Dr Charlie Su, CTO and President of Andes Technology. “We’re empowering our customers to scale AI capabilities across the entire embedded spectrum, from intelligent sensors to multi-core vector processors, ASIL-D certified mission-critical systems and AI acceleration for robots.”
ESWIN Computing (Hall 5, 235) will also be demonstrating why it sees edge AI as the next stage in embedded evolution rather than a separate category. Focusing on smart devices, edge computing infrastructure and automotive electronics, visitors to its stand will see how embedded platforms such as the EIC77 series are evolving from deterministic control systems towards locally processed, inference-driven workloads, whether in connected devices, intelligent industrial deployments or automotive cockpit domains. The emphasis is not on adding AI capability, but on embedding it within architectures that preserve the reliability, latency constraints and energy efficiency that define serious embedded design.
For Dr. Ning He, SVP and CTO of ESWIN Computing, this architectural progression reflects a broader inflection point for the RISC-V ecosystem. “In 2026, driven by its open architecture and scalability, RISC-V will transition from an ‘alternative’ to the default choice for embedded systems”, he says.
See You At Embedded World 2026
What ties all of these threads together is a quiet but significant shift: today’s embedded platforms are expected to support validated toolchains, interoperable software stacks, hardware-level AI inference and operating systems, all of which sit above bare-metal control and what the RISC-V ISA itself describes. Profiles and reference architectures provide architectural guardrails, while ecosystem coordination ensures those guardrails are implemented consistently across vendors and vertical markets. The result is not the abandonment of ‘traditional’ embedded principles, but their extension into more complex, software-rich system contexts.
And what better place to bring all of this together than at Embedded World 2026, which remains “one of the most concentrated forums for technical exchange and ecosystem engagement in our industry”, according to Ozkurt – adding “We look forward to connecting with companies transitioning from RISC-V research to production programs, discussing RISC-V interoperability and ecosystem coordination challenges and of course, strengthening collaboration with partners across silicon, software, and tooling.”
We look forward to welcoming you at the RISC-V Pavilion. But perhaps more significantly, RISC-V will be in a myriad other places throughout the halls: in safety-critical braking systems, smart cockpits, robotics controllers, industrial nodes and intelligent wearables. And those are just the applications we know about. As an open standard available to anyone, we’re constantly discovering new and unexpected use cases at shows like EW that reinforce just how pervasive RISC-V is throughout the embedded landscape today.
See you in Nuremberg.
Embedded World 2026: Panel Sessions
We’re hosting three panel sessions at Embedded World 2026, bringing these themes to life on the Exhibitor Forum Stage in Hall 5.
Automotive Panel
Title: Is the Automotive Industry Ready to Embrace RISC-V?
When: Wednesday 11th, 11:30–12:30
Chaired by Andrea Gallo, CEO of RISC-V International, this panel brings together representatives from Quintauris, Infineon, SiFive, Siemens EDA and Vector to examine whether RISC-V’s rapid growth — now approaching 2.5 billion cores shipped annually — has translated into the ecosystem maturity required by automotive markets. The discussion will address safety qualification, long lifecycle support, toolchain validation, and the architectural shifts underway in software-defined and zonal vehicle platforms.
Embedded Roadmap Panel (Session 1)
Title: Building your future Embedded product roadmap on RISC-V
When: Tuesday, 10:00
Speakers from Siemens, Andes Technology, Semidynamics and SiFive will explore how the inherent flexibility and extensibility of the RISC-V ISA enables differentiated embedded designs across IoT, industrial and AI-enabled systems. The session will examine how customization at the ISA and silicon level is translating into practical roadmap decisions for next-generation embedded products.
Embedded Roadmap Panel (Session 2)
Title: Building your future Embedded product roadmap on RISC-V
When: Wednesday, 15:00
In a second session, speakers from Akeana, Nuclei Systems, Synopsys and DAMO XuanTie will extend the discussion across silicon IP, EDA tooling and software solutions. Together, they will examine how an open, customizable architecture allows companies to address evolving requirements in AI, safety, security, power efficiency and connectivity across the embedded spectrum.
Become a RISC-V Insider
RISC-V Insider is the new way for individuals to stay informed, engaged, and connected to the global RISC-V community. Whether you’re a developer, student, researcher, or enthusiast, RISC-V Insider gives you early access to news, opportunities, and exclusive community experiences.
