At Embedded World this morning, RISC-V International announced approval of its E-Trace (Efficient Trace for Risc-V) and SBI (RISC-V supervisor binary interface) specifications.
E-Trace defines an approach to processor tracing that uses a branch trace, intended for debugging any size of application up to super computers.
The documentation specifies the signals between the RISC-V core and the encoder (or ingress port), a compressed branch trace algorithm, and a packet format to encapsulate compressed branch trace information.
