In an industry where missed corner cases can delay products by weeks or even months, LUBIS EDA recently demonstrated how formal verification can catch critical design bugs early — in some cases, within hours of the verification start.
LUBIS EDA was able to find some undetected bugs that led to RTL changes in a pipelined RISC-V core, adapted and used by a company developing NAND Flash Memory controller. Some of them were detected within the first day.
