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Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies | Breker Verification Systems
RISC-V Takes Embedded World 2022 by Storm | Max Maxfield, Electronic Engineering Journal
German startup MachineWare announces a RISC-V simulator | Scientific Computing World
Esperanto is leading the RISC-V revolution for AI and enabling a new level of AI performance | Esperanto.ai
MachineWare RISC-V simulator for software developers | Brittany Hainzinger, App Developer Magazine
RISC-V International Adds Four ISA Chip Specification Approvals | Todd R Weiss, Futurum Research
Build Open Silicon with Google | Google Open Source Blog
Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP | Joseph Zuckerman, Paolo Mantovani, Davide Giri, Luca P. Carloni
SiFive opens Cambridge RISC-V design centre | Nick Flaherty, EE News Europe
Pine64 Teases RISC-V Based Raspberry Pi Alternative | Ian Evenden, Tom’s HardwareNew startup MachineWare enables ultra-fast RISC-V simulation | Electronic Engineering Journal
OpenHW Group announces RISC-V CORE-V MCU kit | Robin Mitchell, Electropages
Showcasing the key features of the RT-Thread IoT OS and toolchain! | Lance Harvie, RT-Thread IoT OS Global Tech Conference 2021
PUFiot -The Secure Co-processor for RISC-V | PUFsecurity Corp.
AntChain Releases First Self-developed Blockchain Security Chip, the T1 | Pandaily
Vates joins RISC-V International | Vates
We’re closing the gap with Arm and x86, claims SiFive: New RISC-V CPU core for PCs, servers, mobile incoming | Agam Shah, The Register
Meet Snitch: the Small and Agile RISC-V Processor | Michelle Hampson, IEEE Spectrum
M5Stamp C3 RISC-V board supports WiFI 4, Bluetooth 5.0 Long Range and 2 Mbps bitrate | Jean-Luc Aufranc, CNX SoftwareVideo: SMK68 – OpenSource RISCV Custom Mechanical Keyboard | Caesar WuAlibaba open sources four RISC-V cores: XuanTie E902, E906, C906 and C910 | Jean-Luc Aufranc, CNX Software
De-RISC, the H2020 project which will create the first RISC-V fully European platform for aerospace, celebrates its second anniversary | Design and Reuse
Linley Fall Processor Conference 2021 | The Linley Group
The Basics of RISC-V: The Free Open Source Instruction Set | The New Stack
Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies | Breker Verification SystemsBreker Verification Systems, the leading provider of advanced test content synthesis solutions, including RISC-V Cache Coherency and other SoC integration Verification Intellectual Property (VIP) in…
RISC-V Takes Embedded World 2022 by Storm | Max Maxfield, Electronic Engineering JournalI love computers (but only in a manly-man way, you understand). I’m not talking about the end-products that sit on our desks, hang out in…
German startup MachineWare announces a RISC-V simulator | Scientific Computing WorldMachineWare aims to disrupt semiconductor design with the introduction of its high-speed functional simulator, SIM-V. Headquartered in Aachen and emerging from stealth mode in May,…
Esperanto is leading the RISC-V revolution for AI and enabling a new level of AI performance | Esperanto.aiThe ET-SoC-1 inference chip is designed to be the world’s highest performance RISC-V commercial chip, delivering a massively parallel, flexible architecture that combines exceptional performance…
MachineWare RISC-V simulator for software developers | Brittany Hainzinger, App Developer MagazineMachineWare is set to revolutionize semiconductor design with its high-speed functional RISC-V simulator, SIM-V. SIM-V, the company’s flagship product, combines unprecedented simulation performance with exceptional…
RISC-V International Adds Four ISA Chip Specification Approvals | Todd R Weiss, Futurum ResearchRISC-V International Adds Four ISA Chip Specification Approvals Analyst Take: RISC-V International’s latest expansion of its RISC-V ISA specifications and extensions for chip makers is…
Build Open Silicon with Google | Google Open Source BlogTLDR; the Google Hardware Toolchains team is launching a new developer portal, developers.google.com/silicon, to help the developer community get started with its Open MPW shuttle…
Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP | Joseph Zuckerman, Paolo Mantovani, Davide Giri, Luca P. CarloniHeterogeneous, multicore SoC architectures are a critical component of today's computing landscape. However, supporting both increasing heterogeneity and multicore execution are significant design challenges. Meanwhile,…
SiFive opens Cambridge RISC-V design centre | Nick Flaherty, EE News EuropeRISC-V chip designer SiFive has opened its new UK Research & Development (R&D) Centre headquartered in Cambridge. SiFive plans to hire over 100 employees across…
Pine64 Teases RISC-V Based Raspberry Pi Alternative | Ian Evenden, Tom’s HardwarePine64, maker of many fine SBCs including the Rock64 and Quartz64 (opens in new tab), is preparing to dip its toe into the choppy waters…
New startup MachineWare enables ultra-fast RISC-V simulation | Electronic Engineering JournalHeadquartered in Aachen and emerging from stealth mode in May, MachineWare is set to revolutionize semiconductor design with its high-speed functional RISC-V simulator, SIM-V. SIM-V, the company’s…
OpenHW Group announces RISC-V CORE-V MCU kit | Robin Mitchell, ElectropagesRecently at Embedded World 2022, OpenHW demonstrated their latest RISC-V development board that shows off their CORE-V MCU. What advantages will RISC-V present to the…
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Showcasing the key features of the RT-Thread IoT OS and toolchain! | Lance Harvie, RT-Thread IoT OS Global Tech Conference 2021Watch the full video of how the BlueTrum AB32VG1 RISC-V based board creates a great combination. Lance Harvie presents a talk at RT-Thread IoT OS…
PUFiot -The Secure Co-processor for RISC-V | PUFsecurity Corp.Watch the full video of PUFiot -The Secure Co-processor for RISC-V featuring English voice-over and Chinese subtitles.|
AntChain Releases First Self-developed Blockchain Security Chip, the T1 | PandailyAt today’s Apsara Conference, AntChain, the blockchain technology arm of Ant Group, officially released the T1, its first self-developed chip. The chip is equipped with…
Vates joins RISC-V International | VatesVates is proud to announce joining RISC-V International as a Strategic Member. "Strategic members are organizations that are integrating RISC-V and want to have their…
We’re closing the gap with Arm and x86, claims SiFive: New RISC-V CPU core for PCs, servers, mobile incoming | Agam Shah, The RegisterSiFive reckons its fastest RISC-V processor core yet is closing the gap on being a mainstream computing alternative to x86 and Arm. The yet-unnamed high-performance…
Meet Snitch: the Small and Agile RISC-V Processor | Michelle Hampson, IEEE SpectrumTests suggest it is six times faster than other comparable processors. As society's insatiable demand for computing power continues to grow, so too does the…
M5Stamp C3 RISC-V board supports WiFI 4, Bluetooth 5.0 Long Range and 2 Mbps bitrate | Jean-Luc Aufranc, CNX SoftwareIt was only last month that M5Stack launched the M5Stamp Pico module based on an ESP32-PICO-D4 SiP and heat-resistant plastic shell, but M5Stamp C3 board…
Video: SMK68 – OpenSource RISCV Custom Mechanical Keyboard | Caesar WuSMK68:OpenSource RISC-V Custom Mechanical Keyboard with Programmable OLED & Keys, RGB, Hot-swappable, USB/BLE Dual-Mode, even Serial Terminal; SMK68, most Geekery Keyboard for you! Watch the…
Alibaba open sources four RISC-V cores: XuanTie E902, E906, C906 and C910 | Jean-Luc Aufranc, CNX SoftwareAlibaba introduces a range of RISC-V processors in the last few years with the Xuantie family ranging from the E902 micro-controller class core to the…
De-RISC, the H2020 project which will create the first RISC-V fully European platform for aerospace, celebrates its second anniversary | Design and ReuseThe De-RISC Project celebrates its second year through the introduction of a market-ready hardware-software platform based on the RISC-V instruction set architecture (ISA), productizing a…
Linley Fall Processor Conference 2021 | The Linley GroupFor more than a decade, The Linley Group has delivered the industry’s premier processor conferences. This year, the Linley Fall Processor Conference will return to…
The Basics of RISC-V: The Free Open Source Instruction Set | The New StackIn this presentation by Calista Redmond, CEO, & Stephano Cetola, Director of Tech Programs, at Open Source Summit 2021, we explore the basics of RISC-V,…