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RISC-V Shines at Embedded World With New Specs and Processors | Jeff Child, All About Circuits
A RISC-V laptop or mini PC with Rockchip RK3588-class performance may be coming soon | Jean-Luc Aufranc, CNX Software
SiFive X280 RISC-V Processor Gets Scalability, Trust Updates | Todd R. Weiss, Futurum Research
Espressif Launches ESP Privilege Separation, Giving the ESP32-C3 a Secure Split Personality | Gareth Halfcree, Hackster.io
Digi-Key at Embedded World with OpenHardware Group | Digi-Key, Electronic Specifier
De-RISC: A complete RISC-V based space-grade platform | Wessman, Nils-Johan Malatesta, Fabio Ribes, Stefano Andersson, Jan García Vilanova, Antonio Masmano Tello, Miguel Nicolau Gallego, Vicente Gómez Molinero, Paco Le Rhun, Jimmy Alcaide Portet, Sergi Cabo Pitarch, Guillem Bas Jalón, Francisco Benedicte Illescas, PedroMés, Mazzocchetti, Fabio Abella Ferrer, Jaume
Codasip adds Veridify Secure Boot to RISC-V Processors | Veridify Security
Full RISC-V and CMake support added to NECTO Studio 2.0 IDE from MIKROE | Neil Tyler, New Electronics
Freier Befehlssatz als Basis für GPU | Johannes Hiltscher, Golem
Elektor Magazine at Embedded World 2022 | Elektor Magazine
XtremeEDA to enable IoT security deployment with Crypto Quantique’s solution using Codasip’s RISC-V processor | Design and Reuse
RISC-V International emits more open CPU specs | Liam Proven, The Register
Bluespec, Inc. releases ultra-low footprint RISC-V processor family for Xilinx® FPGAs, offers free quick-start evaluation | Bluespec
Codasip Announces UK Hiring for RISC-V Development | Robin Mitchell, ElectroPages
Intel Infuses Nios Soft Processors with RISC-V Instruction Set | Aleksandar Kostovic, Tom’s Hardware
Java port eyed for RISC-V hardware | Paul Krill, InfoWorld
European supercomputer project receives RISC-V test chips | Nick Flaherty, EE News Europe
SiFive HiFive Unmatched Hands-On, Initial RISC-V Performance Benchmarks | Michael Larabel, Phoronix
Chiplet Strategy is Key to Addressing Compute Density Challenges | Balaji Baktha, EE TimesIntel backs RISC-V for Nios FPGA processor | Nick Flaherty, EE News Europe
Security Enclave IP based on RISC-V | Silex Insight
Startup Funding for September 2021 | Jesse Allen, Semiconductor EngineeringSipeed Teases Linux-Capable 64-Bit RISC-V System-on-Module — for Under $20 | Gareth Halfacree, Hackster.io
Initializing RISC-V: A Guided Tour for ARM Developers | Ahmad Fatoum and Rouven Czerwinski, Pengutronix
RISC-V Shines at Embedded World With New Specs and Processors | Jeff Child, All About CircuitsAt Embedded World 2022 today, RISC-V activity heats up as RISC-V International reveals four new spec approvals and SiFive unveils a new version of its…
A RISC-V laptop or mini PC with Rockchip RK3588-class performance may be coming soon | Jean-Luc Aufranc, CNX SoftwareMark Himelstein, Chief Technology Officer, RISC-V International, and Dr. Philipp Tomsich, Chief Technologist & Founder, VRULL GmbH hinted that we may see a RISC-V laptop…
SiFive X280 RISC-V Processor Gets Scalability, Trust Updates | Todd R. Weiss, Futurum ResearchThe News: The latest SiFive X280 RISC-V processor is getting several significant feature updates, including increased scalability up to a 16-core cache-coherent environment, new SiFive…
Espressif Launches ESP Privilege Separation, Giving the ESP32-C3 a Secure Split Personality | Gareth Halfcree, Hackster.ioEspressif has announced a shiny new feature for its ESP32 microcontroller family, starting with the ESP32-C3: privilege separation, designed boost security by keeping user applications…
Digi-Key at Embedded World with OpenHardware Group | Digi-Key, Electronic SpecifierAt Embedded World 2022, on the Digi-Key booth, Paige West speaks with Rick O’Connor, President, and CEO at OpenHardware Group about the company's RISC-V-based CORE-V…
De-RISC: A complete RISC-V based space-grade platform | Wessman, Nils-Johan Malatesta, Fabio Ribes, Stefano Andersson, Jan García Vilanova, Antonio Masmano Tello, Miguel Nicolau Gallego, Vicente Gómez Molinero, Paco Le Rhun, Jimmy Alcaide Portet, Sergi Cabo Pitarch, Guillem Bas Jalón, Francisco Benedicte Illescas, PedroMés, Mazzocchetti, Fabio Abella Ferrer, JaumeThe H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain…
Codasip adds Veridify Secure Boot to RISC-V Processors | Veridify SecurityCodasip, the leader in customizable RISC-V processor IP and processor design automation, today announced that quantum-resistant secure tools from Veridify Security Inc. are now available…
Full RISC-V and CMake support added to NECTO Studio 2.0 IDE from MIKROE | Neil Tyler, New ElectronicsVersion 2.0 adds full RISC-V support and CMake project-native support, plus significant Editor, Designer & Code Model improvements. The NECTO Studio 2.0 is a complete,…
Freier Befehlssatz als Basis für GPU | Johannes Hiltscher, GolemSeit 2009 entwickelt Think Silicon in Griechenland Grafikhardware. Auf der Embedded World 2022 in Nürnberg stellt das Unternehmen seine Produkte vor. Während die Nema-GPUs für…
Elektor Magazine at Embedded World 2022 | Elektor MagazineDownload the digital version featuring RISC-V.
XtremeEDA to enable IoT security deployment with Crypto Quantique’s solution using Codasip’s RISC-V processor | Design and ReuseXtremeEDA is a leading North American design and functional verification services provider to the ASIC, SoC, and FPGA hardware industry today announced that it has…
RISC-V International emits more open CPU specs | Liam Proven, The RegisterRISC-V International has grown its pile of royalty-free, open specifications, with additional documents covering firmware, hypervisors, and more. RISC-V – pronounced "risk five", and not…
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Bluespec, Inc. releases ultra-low footprint RISC-V processor family for Xilinx® FPGAs, offers free quick-start evaluation | BluespecBluespec, Inc., a founding member of RISC-V International and supplier of RISC-V Processor IP and tools, released the MCU RISC-V processor family targeted at ultra-low…
Codasip Announces UK Hiring for RISC-V Development | Robin Mitchell, ElectroPagesRecently, RISC-V development Codasip announced that it will be looking to hire 100 engineers in the UK to continue its development with RISC-V IP cores.…
Intel Infuses Nios Soft Processors with RISC-V Instruction Set | Aleksandar Kostovic, Tom’s HardwareIntel updated its lineup of the famous Nios soft processors with the latest Nios V softcore, designed around the open-source RISC-V instruction set architecture. The Nios…
Java port eyed for RISC-V hardware | Paul Krill, InfoWorldPort of the JVM to the open-source licensed instruction set architecture could be ready later this year, if project gets approval to proceed. The RISC-V…
European supercomputer project receives RISC-V test chips | Nick Flaherty, EE News EuropeThe EPI project has 28 partners from 10 European countries, with the goal of making EU achieve independence in HPC chip technologies and HPC infrastructure.…
SiFive HiFive Unmatched Hands-On, Initial RISC-V Performance Benchmarks | Michael Larabel, PhoronixA few weeks ago I finally received the HiFive Unmatched from SiFive as their flagship RISC-V development board. As a reminder this is their mini-ITX…
Chiplet Strategy is Key to Addressing Compute Density Challenges | Balaji Baktha, EE TimesData center workloads are quickly evolving, demanding high compute density with varying mixes of compute, memory and IO capability. This is driving architectures that are…
Intel backs RISC-V for Nios FPGA processor | Nick Flaherty, EE News EuropeIntel's Nios V soft processor for its FPGAs uses the RISC-V: RV32IA architecture with atomic extensions, 5-stage pipeline and AXI4 interfaces. Intel has developed a…
Security Enclave IP based on RISC-V | Silex InsightSee the latest brochure from Silex Insights on security enclave IP based on RISC-V. See the full brochure.
Startup Funding for September 2021 | Jesse Allen, Semiconductor EngineeringStartups focused on data center chips had a big month in September. A new emergent from stealth promises to accelerate big data analytics, and startups…
Sipeed Teases Linux-Capable 64-Bit RISC-V System-on-Module — for Under $20 | Gareth Halfacree, Hackster.ioSipeed has released details on a new system-on-module board built around the RISC-V Allwinner D1 chip — and it's aiming to bring the Linux-capable device…
Initializing RISC-V: A Guided Tour for ARM Developers | Ahmad Fatoum and Rouven Czerwinski, PengutronixRISC-V is the hot and upcoming architecture in the embedded space. While a majority of embedded developers have earned their chops programming for ARM processors…