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Redpine Founder Launches AI Processor Startup | Sally Ward-Foxton, EE Times
Ceremorphic addresses AI, HPC, and the metaverse with QS 1 chip, lands $50M | Arne Verheyde, Venture Beat
RISC-V CH32V307 QuickStart E01 | WCH
$10 RISC-V Development Board is an Arduino Alternative | Ian Evenden, Tom’s Hardware
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors | Nazareno Bruschi∗ , Germain Haugou†‡, Giuseppe Tagliavini∗ , Francesco Conti∗ , Luca Benini∗†, and Davide Rossi∗ (∗University of Bologna, †ETH, ‡GreenWaves-Technologies)SiFive Preps Next-Gen HiFive Unmatched RISC-V Boards | Anton Shilov, Tom’s Hardware
Google Research Releases Circuit Training, an Open-Source Framework for Automated Chip Floorplanning | Gareth Halfacree, AB Open
NSITEXE and Green Hills Software Partner on RISC-V Solutions | Design & ReuseASIC roundup of open source RISC-V CPU cores | Oguz Meteer, BitlogIT
RISC-V SoC + AI – Run a demo of the ncnn inference framework using Allwinner’s D1 “Nezha” Development Board | Verimake
The State of the RISC-V Union, part II | Paul McLellan, Cadence Design Systems
First impression on Nezha RISC-V SBC | 3mdeb
Video: Glitching RISC-V chips: MTVEC corruption for hardening ISA | Adam Zabrocki and Alex Matrosov, DEF CON 29
Open source SystemVerilog tools in ASIC designOpen source SystemVerilog tools in ASIC design
Video: OSDI 21 – The nanoPU: A Nanosecond Network Stack for Datacenters
Hands-On: Whiskey Pirates DC29 Hardware Badge Blings With RISC-V | Mike Szczys, Hackaday
Huawei Release Their First RISC-V Development System – Hi3861 | Robin Mitchell, electropages
The RISC-V Platform Specification aims to ensure RISC-V hardware and software compatibility | Jean-Luc Aufranc, CNX Software
Video: Next-Generation Vector Processor Design II | Dr. Thang Tran, Andes TechnologyBL-63B – A smaller BL602 IoT module that sells for $1.5 | Jean-Luc Aufranc, CNX SoftwareRadxa and StarFive Partner to Deliver RISC-V Single Board PC to Consumers | Aleksandar Kostovic, Tom’s HardwareVideo: QEMU RV32I Installation & Setup | John’s Basement
NSI-TEXE achieves world’s first RISC-V processor with vector extension certified for ISO 26262 ASIL D ready product
Redpine Founder Launches AI Processor Startup | Sally Ward-Foxton, EE TimesCeremorphic, an AI chip startup emerging from stealth mode this week, is readying a heterogeneous AI processor aimed at model training in data centers, automotive,…
Ceremorphic addresses AI, HPC, and the metaverse with QS 1 chip, lands $50M | Arne Verheyde, Venture BeatToday, Ceremorphic, a startup, is coming out of stealth mode with $50 million of series A funding along with the announcement of the QS 1 chip,…
RISC-V CH32V307 QuickStart E01 | WCHMake RISC-V MCU development more convenient. Watch the full video.
$10 RISC-V Development Board is an Arduino Alternative | Ian Evenden, Tom’s HardwareA new RISC-V board out of China boasts eight UART interfaces and is looking for community involvement with its firmware. RISC-V boards come in many…
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors | Nazareno Bruschi∗ , Germain Haugou†‡, Giuseppe Tagliavini∗ , Francesco Conti∗ , Luca Benini∗†, and Davide Rossi∗ (∗University of Bologna, †ETH, ‡GreenWaves-Technologies)Abstract—The last few years have seen the emergence of IoT processors: ultra-low power systems-on-chips (SoCs) combining lightweight and flexible micro-controller units (MCUs), often based on…
SiFive Preps Next-Gen HiFive Unmatched RISC-V Boards | Anton Shilov, Tom’s HardwareSiFive is ending production of current-generation Unmatched boards for RISC-V developers. SiFive this week announced that due to challenges with components supply, it would discontinue…
Google Research Releases Circuit Training, an Open-Source Framework for Automated Chip Floorplanning | Gareth Halfacree, AB OpenGoogle Research has released the source code for a chip floor-plan generate based on deep reinforcement learning – after publishing a paper demonstrating how effective…
NSITEXE and Green Hills Software Partner on RISC-V Solutions | Design & ReuseNSITEXE, Inc., a wholly owned subsidiary of Denso Corporation that develops and sells high efficiency processor IP for embedded systems, and Green Hills Software, the…
ASIC roundup of open source RISC-V CPU cores | Oguz Meteer, BitlogITWhile waiting for simulation results for my final paper, I thought I’d synthesize and do place & route of several open source RISC-V CPU cores for fun.…
RISC-V SoC + AI – Run a demo of the ncnn inference framework using Allwinner’s D1 “Nezha” Development Board | VerimakeD1 is Allwinner's first SoC based on the RISC-V ISA,which has a 64-bit Xuantie C906 core from T-Head. The "Nezha" Development Board is an AIoT development board based on the…
The State of the RISC-V Union, part II | Paul McLellan, Cadence Design SystemsThis is part 2 of my post on DAC and RISC-V from December. The first post is here. This post will cover Krste's presentation and then…
First impression on Nezha RISC-V SBC | 3mdebNezha board is a development board that is designed by an AWOL. This project uses a D1 SoC from Allwinner which is used for the…
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Video: Glitching RISC-V chips: MTVEC corruption for hardening ISA | Adam Zabrocki and Alex Matrosov, DEF CON 29View the full video and description on the DEF CON YouTube Channel. Presentation Summary: RISC-V is an open standard instruction set architecture (ISA) provided under…
Open source SystemVerilog tools in ASIC designOpen source SystemVerilog tools in ASIC designOpen source hardware is undeniably undergoing a renaissance whose origin can be traced to the establishment of RISC-V Foundation (later redubbed RISC-V International). The open…
Video: OSDI 21 – The nanoPU: A Nanosecond Network Stack for DatacentersThe nanoPU: A Nanosecond Network Stack for Datacenters by Stephen Ibanez, Alex Mallery, Serhat Arslan, and Theo Jepsen, Stanford University; Muhammad Shahbaz, Purdue University; Changhoon…
Hands-On: Whiskey Pirates DC29 Hardware Badge Blings With RISC-V | Mike Szczys, HackadayThe Whiskey Pirates have once again dropped an excellent electronic badge for DEF CON 29. This is, of course, unofficial, but certainly makes the list…
Huawei Release Their First RISC-V Development System – Hi3861 | Robin Mitchell, electropagesRecently, Huawei released their first RISC-V development system to help engineers use the HarmonyOS operating system targeted at IoT devices. So why is Huawei looking…
The RISC-V Platform Specification aims to ensure RISC-V hardware and software compatibility | Jean-Luc Aufranc, CNX SoftwareOriginally published in CNX Software - Embedded Systems News Written by Jean-Luc Aufranc (and contributions via Drew Fustini) The RISC-V platform specification aims to define…
Video: Next-Generation Vector Processor Design II | Dr. Thang Tran, Andes Technology2021 Andes RISC-V CON Webinar Next-Generation Vector Processor Design II by Speaker: Thang Tran, Principal Architect, Andes Technology The event is the second of a…
BL-63B – A smaller BL602 IoT module that sells for $1.5 | Jean-Luc Aufranc, CNX SoftwareBouffalo Labs BL602 is a low-cost, low-power RISC-V microcontroller that offers 2.4 GHz WiFi and Bluetooth 5.0 LE connectivity for IoT projects for about the price of…
Radxa and StarFive Partner to Deliver RISC-V Single Board PC to Consumers | Aleksandar Kostovic, Tom’s HardwareRISC-V is a novel processor instruction set architecture (ISA) developed at UC Berkely. Originally designed for teaching purposes, the ISA has been released as an…
Video: QEMU RV32I Installation & Setup | John’s BasementSee a demonstration from John's Basement YouTube channel for a tutorial on installing and testing the GNU RISC-V toolchain and qemu on Ubuntu 20.04 for…
NSI-TEXE achieves world’s first RISC-V processor with vector extension certified for ISO 26262 ASIL D ready productThe DR1000C, a data flow processor (DFP) developed by NSITEXE, Inc. (headquartered in Minato Ward, Tokyo, Japan; President and CEO: Yukihide Niimi; hereinafter “NSITEXE”) has…