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SEGGER J-Link – Performance analysis on RISC-V | SEGGER
At CES2022 Bouffalo Shows its Matter Turnkey Solution | Bouffalo Lab, EE Times
Deep Vision Adopts SiFive RISC-V to Add OpenCV-Enabled AI Support | SiFive
Picoclick C3T Is the World’s Smallest IoT Button and It Has a RISC-V Processor | James Lewis, Hackster.io
Baikal Electronics allies with IP-cores domestic developer | Design & Reuse
Tang Nano 9K FPGA board can emulate PicoRV32 RISC-V soft-core with all peripherals | Jean-Luc Aufranc, CNX Software
RISC-V MCU CH32V307 Tutorial — Voice Control DEMO | Verimake
CFU Playground: Customize Your ML Processor for Your Specific TinyML Model | Tim Callahan, TinyML TalksThe Rapid Rise of RISC-V | Jack Kang, SiFive
ZAYA Secure μContainers for RISC-V Microcontrollers | Zaya
RISC-V SoCs: Powering Embedded Computing | Efinix, Inc.
“Revolutionizing Computer Architecture” – A fireside chat Dr. David Patterson, Vice Chair of RISC-V | Shaastra IITM
Post-quantum chip has built-in hardware Trojan | Christoph Hammerschmidt, EE News Europe
Video: RISC-V RV32I R-Type | Maven Silicon
Custom RISC-V Processor Built in VHDL | Bryan Cockfield, Hackaday
Ingenic T40, focusing on the new SVIoT track | Muzi, Leiphone.com
Video: EKF for a 9-DOF IMU on a RISC-V MCU | Hien VuDesigning a RISC-V CPU, Part 1: Learning hardware design as a software engineer | Hannah McLaughlinSERV : RISC-V for a fistful of gates | Diode Zone
RISC-V Verification: The 5 Levels Of Simulation-Based Processor Hardware DV | By Lee Moore and Simon Davidmann, Semiconductor Engineering
ESP32-H2 Bluetooth LE & 802.15.4 RISC-V SoC shows up in ESP-IDF source code | Jean-Luc Aufranc
The 2021 RISC-V Summit to Co-Locate with the 58th Design Automation Conference (DAC) in San Francisco | Yahoo! FinanceEspressif’s Unannounced RISC-V ESP32-H2 LR-WPAN SoC Leaks in an SDK Update | Gareth Halfacree, Hackster.io
Is RISC-V the Future? | Codasip
SEGGER J-Link – Performance analysis on RISC-V | SEGGERWatch how to do a performance analysis on a RISC-V device using SEGGER's market-leading J-Link, Ozone and SystemView to tap into SiFive's insight debug and…
At CES2022 Bouffalo Shows its Matter Turnkey Solution | Bouffalo Lab, EE TimesWith a comprehensive lineup of wireless SOCs, Bouffalo Lab fully supports Matter, the wireless and interoperability standard for smart home devices, offering a complete turnkey…
Deep Vision Adopts SiFive RISC-V to Add OpenCV-Enabled AI Support | SiFiveSiFive, Inc., the founder and leader of RISC-V computing, today announced that Deep Vision will integrate SiFive RISC-V processor IP into its next-generation inference accelerators to enable…
Picoclick C3T Is the World’s Smallest IoT Button and It Has a RISC-V Processor | James Lewis, Hackster.ioProgrammable button supports single, multiple, and long presses while sipping only 3 uA when idle. WiFi-enabled buttons send an MQTT message or REST call from…
Baikal Electronics allies with IP-cores domestic developer | Design & Reuse“Varton Group” (“Baikal Electronics” & “Astra Linux Group” shareholder) acquires a stake in Russian developer of RISC-V based IP processor cores - CloudBEAR Company. Supporting…
Tang Nano 9K FPGA board can emulate PicoRV32 RISC-V soft-core with all peripherals | Jean-Luc Aufranc, CNX SoftwareTang Nano 9K FPGA is the third board from Sipeed based on GOWIN FPGA following the original Tang Nano board with 1K LUT and Tang Nano 4K launched last…
RISC-V MCU CH32V307 Tutorial — Voice Control DEMO | VerimakeRISC-V MCU CH32V307 Tutorial — Voice Control DEMO Configuration of the Development Environment DEMO Programme Procedure Description See the full tutorial.
CFU Playground: Customize Your ML Processor for Your Specific TinyML Model | Tim Callahan, TinyML TalksCFU (Custom Function Unit) Playground lets you build your own specialized & optimized ML processor based on the RISC-V ISA, implemented on an FPGA using…
The Rapid Rise of RISC-V | Jack Kang, SiFiveSiFive is aiming high with bold new technology for performance-driven applications. SiFive transformed in 2021 and grew from leading RISC-V for embedded products into performance-demanding…
ZAYA Secure μContainers for RISC-V Microcontrollers | ZayaMarking a key milestone in IoT security, Zaya has announced Secure Containers for RISC-V Microcontrollers. Containers are useful tools provided by Rich Operating Systems such…
RISC-V SoCs: Powering Embedded Computing | Efinix, Inc.RISC-V is an open-source standard instruction set architecture (ISA) that is managed by the non-profit RISC-V Foundation. This modular ISA has a base instruction set and…
“Revolutionizing Computer Architecture” – A fireside chat Dr. David Patterson, Vice Chair of RISC-V | Shaastra IITMThe advent of the 20th century saw an evolution like no other. At the heart of this evolution lies the ability of an instrument to…
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Post-quantum chip has built-in hardware Trojan | Christoph Hammerschmidt, EE News EuropeA team at the Technical University of Munich (TUM) has created a computer chip that implements post-quantum cryptography particularly effectively. In future, such chips could…
Video: RISC-V RV32I R-Type | Maven SiliconThis video explains the RV32I R-Type instructions. To know more, explore Maven Silicon's RISC-V courses. Watch the full video on YouTube.
Custom RISC-V Processor Built in VHDL | Bryan Cockfield, HackadayWhile ARM continues to make inroads into the personal computing market against traditional chip makers like Intel and AMD, it’s not a perfect architecture and…
Ingenic T40, focusing on the new SVIoT track | Muzi, Leiphone.com"Jun is the first chip company to focus on the SVIoT track wholeheartedly, and provide full-stack core technologies such as chips, AI computing power, development…
Video: EKF for a 9-DOF IMU on a RISC-V MCU | Hien VuIn this video see Hien Vu demonstrate extended Kalman Filter calculation being carried out by the MCU. Calibration was done using python. Huge thanks to…
Designing a RISC-V CPU, Part 1: Learning hardware design as a software engineer | Hannah McLaughlinI have no experience in digital logic design. That is, I didn't until I recently decided that I would like to try designing my own…
SERV : RISC-V for a fistful of gates | Diode ZoneThe award-winning SERV is the world's smallest RISC-V CPU. It's the perfect companion whenever you need a bit of computation and silicon real estate is…
RISC-V Verification: The 5 Levels Of Simulation-Based Processor Hardware DV | By Lee Moore and Simon Davidmann, Semiconductor EngineeringThe RISC-V open standard ISA (Instruction Set Architecture) offers developers the opportunity to configure the features and functions of a custom processor to uniquely address…
ESP32-H2 Bluetooth LE & 802.15.4 RISC-V SoC shows up in ESP-IDF source code | Jean-Luc AufrancEspressif Systems is working on yet another RISC-V chip with ESP32-H2 SoC offering Bluetooth LE and 802.15.4 connectivity showing up in the ESP-IDF framework source…
The 2021 RISC-V Summit to Co-Locate with the 58th Design Automation Conference (DAC) in San Francisco | Yahoo! FinanceRISC-V International and the Design Automation Conference (DAC) today announced the co-location of the 2021 RISC-V Summit with the 58th DAC at Moscone West in San Francisco in December…
Espressif’s Unannounced RISC-V ESP32-H2 LR-WPAN SoC Leaks in an SDK Update | Gareth Halfacree, Hackster.ioEight months after a leak pre-empted the launch of the ESP32-C3, Espressif's first part to use a RISC-V core as its central processor, a new…
Is RISC-V the Future? | CodasipIs RISC-V the future? This is a question that we often get asked, and let’s assume that we mean ‘is the RISC-V going to be…