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RISC-V Summit 2021 | Codasip
Ventana reveals RISC-V CPU compute chiplet for data center | Nitin Dahad, Embedded.com
IAR Systems appoints Richard Lind as CEO | IAR Systems
RISC-V wants to be the third major chip architecture. CEO Calista Redmond has a lot of work to do | Max A. Cherney, Protocol
Finnish consortium tapes out multicore RISC-V edge AI IoT chip | Nick Flaherty, EE News Europe
HiSilicon Hi3731V110 32-bit RISC-V processor is made for Full HD televisions | Jean-Luc Aufranc, CNX Software
The 2021 RISC-V Summit Charts the Wildfire Expansion of Open-source Hardware | Tyler Charboneau, All About CircuitsStarFive Dubhe 64-bit RISC-V core to be found in 12nm, 2 GHz processors | Jean-Luc Aufranc, CNX Software
Chatter around GPUs for RISC-V is growing | Agam Shah, The Register
RISC-V vector instructions support in Renode | AntmicroStarFive VisionFive single board computer officially for sale, accelerating RISC-V ecosystem development | Sponsored, CNX Software
Huawei HiSilicon Hi3731V110 is a new FHD TV chip based on RISC-V architecture | Sudarshan, GizmoChina
DC-SCM compatible open source BMC hardware platform | Antmicro
Video: Exception handling in a RISC-V core – Exercise #7 | Learn RISC-V
Announcing the Research Triangle RISC-V Community Group | Daniel Mangum
Week In Review: Design, Low Power | Jesse Allen, Semiconductor Engineering
Andes Technology Announces Over 2 Billion Shipments Of Andes-Embedded SoCs In 2020
Video: Spike & Proxy Kernel from Source to Hello World | Danny PratamaVideo: Spike Debugging, OpenOCD, and GDB | Danny PratamaVideo: GCC Toolchain & SiFive Prebuilt Toolchain | Derry Pratama
SiFive Collaborates with Imperas on Models of SiFive’s RISC-V Core IP Portfolio
Deep neural networks… IN SPAAACE: Vector-enhanced RISC-V chips could give satellites onboard AI | Gareth Halfacree, The Register
SiFive Performance P550 Core Sets New Standard as Highest Performance RISC-V Processor IPAdvanced co-simulation with Renode and Verilator: PolarFire SoC and FastVDMA | Antmicro
RISC-V Summit 2021 | CodasipWe weren’t sure what to expect from our first major attendance at a #RISCVSummit. Although we were a founding member of RISC-V - as we’ve…
Ventana reveals RISC-V CPU compute chiplet for data center | Nitin Dahad, Embedded.comThe new Ventana Veyron V1 RISC-V CPU core running at 3.6GHz in 5nm is the centerpiece of a compute chiplet solution with chiplets supplied by…
IAR Systems appoints Richard Lind as CEO | IAR SystemsUppsala, Sweden—December 13, 2021—IAR Systems, the world leader in software tools and services for embedded development, presented its new CEO. The board of directors of…
RISC-V wants to be the third major chip architecture. CEO Calista Redmond has a lot of work to do | Max A. Cherney, ProtocolRISC-V backers think its open-source chip cores could be a viable alternative to chips made by Intel, AMD and Arm’s partners. It will be an…
Finnish consortium tapes out multicore RISC-V edge AI IoT chip | Nick Flaherty, EE News EuropeBallast, the first multicore RISC-V System on Chip (SoC) developed by the SoC Hub led by Nokia and Tampere University, has taped out in a…
HiSilicon Hi3731V110 32-bit RISC-V processor is made for Full HD televisions | Jean-Luc Aufranc, CNX SoftwareWe’ve previously covered Hisilicon Hi3861V100 32-bit RISC-V microcontroller, but HiSilicon Hi3731V110 32-bit RISC-V processor designed for Full HD televisions, the company has gone up the scale with…
The 2021 RISC-V Summit Charts the Wildfire Expansion of Open-source Hardware | Tyler Charboneau, All About CircuitsIf 2021's RISC-V Summit told us anything, it's that the open-source hardware movement isn't slowing down anytime soon. With this year’s RISC-V Summit officially concluded, open-source processors are…
StarFive Dubhe 64-bit RISC-V core to be found in 12nm, 2 GHz processors | Jean-Luc Aufranc, CNX SoftwareStarFive has just announced customers’ delivery of the 64-bit RISC-V Dubhe core based on RV64GC ISA plus bit manipulation, user-level interrupts, as well as the…
Chatter around GPUs for RISC-V is growing | Agam Shah, The RegisterThe activity around creating a legit graphics processor for RISC-V chip designs, an emerging competitor to x86 and ARM, is gaining steam. Special interest groups…
RISC-V vector instructions support in Renode | AntmicroBuilding on top of the flexibility that was the original premise of Renode, our open source simulation framework has for some years now been used for…
StarFive VisionFive single board computer officially for sale, accelerating RISC-V ecosystem development | Sponsored, CNX SoftwareSan Francisco, U.S. – Dec. 8, 2021- at RISC-V Summit 2021, StarFive Technology Co., Ltd. (hereinafter “StarFive”), the leader of RISC-V software and hardware ecosystem…
Huawei HiSilicon Hi3731V110 is a new FHD TV chip based on RISC-V architecture | Sudarshan, GizmoChinaHiSilicon is a Huawei-owned semiconductor company. It is known for Kirin-branded mobile SoCs that once powered a myriad of HUAWEI and HONOR smartphones. This division has now announced a…
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DC-SCM compatible open source BMC hardware platform | AntmicroOpen source software is omnipresent in the server and cloud world, with open source operating systems, container runtimes, as well as frameworks for device management,…
Video: Exception handling in a RISC-V core – Exercise #7 | Learn RISC-VThis video demonstrates load access fault exception generation and handling. It discusses the basic registers associated and configuring those. Watch the full video tutorial here. …
Announcing the Research Triangle RISC-V Community Group | Daniel MangumI am excited to announce the launch of the Research Triangle RISC-V Community Group! As evidenced by my recent posts and conference talks, I have been spending more and…
Week In Review: Design, Low Power | Jesse Allen, Semiconductor EngineeringTools Imperas and Valtrix inked a multi-year distribution and support agreement that makes Imperas simulation technology and RISC-V reference models available pre-integrated within Valtrix STING for RISC-V processor verification.…
Andes Technology Announces Over 2 Billion Shipments Of Andes-Embedded SoCs In 2020Andes Technology (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores, announced a remarkable record of 2 billion annual SoC shipments…
Video: Spike & Proxy Kernel from Source to Hello World | Danny PratamaSee Danny Pratama's step-by-step tutorial for running SPIKE Simulator with Proxy Kernel. This tutorial assumes you already have compiler for RISC-V. Watch the full tutorial…
Video: Spike Debugging, OpenOCD, and GDB | Danny PratamaIn this tutorial Danny Pratama will explain step by step how to use SPIKE internal debugger or with GDB using OpenOCD Watch the full tutorial…
Video: GCC Toolchain & SiFive Prebuilt Toolchain | Derry PratamaIn this tutorial Danny Pratama will explain the steps to compiling your own RISC-V GNU toolchain or use the prebuilt toolchain by SiFive Watch the…
SiFive Collaborates with Imperas on Models of SiFive’s RISC-V Core IP PortfolioImperas Software Ltd.,a leader in virtual platforms and high-performance software simulation, today announced that SiFive, Inc., an industry leader in RISC-V processors and silicon solutions,…
Deep neural networks… IN SPAAACE: Vector-enhanced RISC-V chips could give satellites onboard AI | Gareth Halfacree, The RegisterBoffins from the Delft University of Technology (TU Delft) and European Space Agency (ESA) have penned a paper detailing the design of a processor they…
SiFive Performance P550 Core Sets New Standard as Highest Performance RISC-V Processor IPNew SiFive Performance Family of application processors offers best in class performance, area, and efficiency for a wide variety of markets SAN MATEO, Calif., June…
Advanced co-simulation with Renode and Verilator: PolarFire SoC and FastVDMA | AntmicroCo-simulating HDL has been possible in Renode since the 1.7.1 release, but the functionality - critical for hardware/software co-development as well as FPGA use cases…