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HLK-W801 board features Alibaba Xuantie XT804 based MCU with WiFi 4, Bluetooth LE 4.2 | Jean-Luc Aufranc, CNX Software
MIPS selects Imperas Reference Models for RISC-V Processor Verification | Imperas
Embedded vision kit employs SoC FPGA | Susan Nordyk, EDN
Implementing Bluetooth® BIS and CIS LE Audio | Telink Staff
RISC-V is Inevitable | Jack Kang, SiFive
Accelerating the Future of RISC-V | Rohit Kumar, SiFiveMeet ESP-C3-M1 and ESP-C3-M1-I ultra small ESP32-C3 mini modules | CNX Software, Sponsored
Video: RISC-V Duisburg Group – Making an authentication token IC based on the Opentitan Project
In Hardware We Trust? From TPM to Enclave Computing on RISC-V | Emmanuel Stapf, Patrick Jauernig, Ferdinand Brasser, and Ahmad-Reza Sadeghi
Samsung-Esperanto Concept AI-SSD Prototype | David Schor, WikiChip Fuse
Canonical at RISC-V Summit 2021 | Canonical
Embedded edge vision development kit for RISC-V FPGA | Nick Flaherty, EE News Europe
Deploying deep learning models on the edge with Kenning
Intel Will Offer SiFive RISC-V CPUs on 7nm, Plans Own Dev Platform | Joel Hruska, ExtremeTech
Bluetrum Launches RT-Thread-Based Arduino Uno-Like RISC-V Development Board, the AB32VG1 | Gareth Halfacree, hackster.io
Video: Arm vs RISC-V-What You Need to Know | Gary Explains
EPI Chair Jean-Marc Denis Shares Vision for Future Supercomputers | Tiffany Trader
Intel to Adopt SiFive’s New High-Performance P550 RISC-V Cores With 7nm Platform | Paul Alcorn, Tom’s Hardware
NEORV32: a customizable RISC-V SoC #RISCV #FPGA
SiFive Boasts of the “Highest-Performance RISC-V Processor” in Its New P550 Design | Gareth Halfacree, hackster.ioCanonical enables Ubuntu on SiFive’s HiFive RISC-V boardsExtended development tools performance capabilities for Andes RISC-V cores
IAR Systems extends development tools performance capabilities for Andes RISC-V cores
Intel to Adopt SiFive’s New High-Performance P550 RISC-V Cores With 7nm Platform | Paul Alcorn, Tom’s Hardware
HLK-W801 board features Alibaba Xuantie XT804 based MCU with WiFi 4, Bluetooth LE 4.2 | Jean-Luc Aufranc, CNX SoftwareEarlier this month, we wrote about the 240 MHz WinnerMicro W806 Alibaba Xuantie XT804 C-Sky microcontroller with 1MB flash, 288KB SRAM found in the $2…
MIPS selects Imperas Reference Models for RISC-V Processor Verification | ImperasImperas RISC-V golden reference models and Verification IP used for functional RISC-V Processor Verification and Architectural Compatibility Testing. Imperas Software Ltd., the leader in RISC-V simulation…
Embedded vision kit employs SoC FPGA | Susan Nordyk, EDNMicrochip’s Smart Embedded Vision development platform is a full-featured kit for designing with PolarFire RISC-V SoC FPGAs. The platform enables the design of secure, reliable,…
Implementing Bluetooth® BIS and CIS LE Audio | Telink StaffTelink’s Broadcast Isochronous Stream (BIS) and Connected Isochronous Stream (CIS) LE Audio solutions change the way we experience audio and connect with the world around…
RISC-V is Inevitable | Jack Kang, SiFiveIn just a few short years, RISC-V has become a category of utmost importance in tech; but, things are just getting started. In 2014, the…
Accelerating the Future of RISC-V | Rohit Kumar, SiFiveThe freedom of RISC-V enables a bright future for SiFive. What a time to be in the Semiconductors and CPU industry! As an industry, we…
Meet ESP-C3-M1 and ESP-C3-M1-I ultra small ESP32-C3 mini modules | CNX Software, SponsoredHalf-year ago, Ai-Thinker launched new ESP32-C3 series modules that are fully pin-to-pin compatible with ESP8266, namely ESP-C3-12F, ESP-C3-32S, ESP-C3-01M, ESP-C3-13, ESP-C3-13U. After several months, the…
Video: RISC-V Duisburg Group – Making an authentication token IC based on the Opentitan ProjectSee Johann Heyszl speaking at the RISC-V Duisburg 4th community event on making an authentication token IC based on the Open Titan Project. Watch the…
In Hardware We Trust? From TPM to Enclave Computing on RISC-V | Emmanuel Stapf, Patrick Jauernig, Ferdinand Brasser, and Ahmad-Reza SadeghiAbstract: System-on-Chip platforms have been increasingly extended with trusted computing functionality to provide strong protection for sensitive software applications through enclaves that only require trust…
Samsung-Esperanto Concept AI-SSD Prototype | David Schor, WikiChip FuseEarlier this year we’ve detailed Esperanto’s first neural processor, the ET-SoC-1. The company’s approach for accelerating AI workloads involved integrating a large number of tiny…
Canonical at RISC-V Summit 2021 | CanonicalRISC-V Summit is an annual conference that showcases the power that open collaboration can have on the processor industry. This year, the event is taking…
Embedded edge vision development kit for RISC-V FPGA | Nick Flaherty, EE News EuropeThe Smart Embedded Vision tool for Microchip’s PolarFire RISC-V FPGA supports vision applications from neural network inferencing to Industrial Internet of Things (IIoT) and factory…
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Deploying deep learning models on the edge with KenningThe demand for deploying machine learning models, especially state-of-the-art deep neural networks on edge devices is rapidly growing. Edge AI allows to run inference locally,…
Intel Will Offer SiFive RISC-V CPUs on 7nm, Plans Own Dev Platform | Joel Hruska, ExtremeTechIntel and SiFive made a pair of announcements yesterday that underscore how serious the chip giant is about ramping its own foundry services. First, Intel…
Bluetrum Launches RT-Thread-Based Arduino Uno-Like RISC-V Development Board, the AB32VG1 | Gareth Halfacree, hackster.ioSub-$13 system comes with RT-Thread Studio IDE support, audio capabilities, and even an infrared receiver. Chinese electronics specialist Bluetrum has announced the launch of a…
Video: Arm vs RISC-V-What You Need to Know | Gary ExplainsArm is a RISC Instruction Set Architecture (ISA) and simultaneously a company that designs RISC CPU cores. RISC-V is also a RISC ISA, but not…
EPI Chair Jean-Marc Denis Shares Vision for Future Supercomputers | Tiffany TraderIn this video interview with HPCwire’s Managing Editor Tiffany Trader, Jean-Marc Denis, European Processor Initiative (EPI) chair of the board and head of strategy at…
Intel to Adopt SiFive’s New High-Performance P550 RISC-V Cores With 7nm Platform | Paul Alcorn, Tom’s HardwareSiFive, the leading designer of chips based on the open source RISC-V architecture, announced its new SiFive Performance line of chips today that support 64-bit…
NEORV32: a customizable RISC-V SoC #RISCV #FPGAThe NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary…
SiFive Boasts of the “Highest-Performance RISC-V Processor” in Its New P550 Design | Gareth Halfacree, hackster.ioCompany claims its latest part is the highest-performing RISC-V core around — but won't be releasing the design under an open license. RISC-V pioneer SiFive…
Canonical enables Ubuntu on SiFive’s HiFive RISC-V boardsWith Canonical announcing Ubuntu support for so much new hardware, the announcement of Ubuntu ported to a new architecture can go unnoticed. But today, we…
Extended development tools performance capabilities for Andes RISC-V coresExtended development tools performance capabilities for Andes RISC-V cores Latest version of IAR Embedded Workbench for RISC-V adds support for latest Andes RISC-V processor technology,…
IAR Systems extends development tools performance capabilities for Andes RISC-V coresLatest version of IAR Embedded Workbench for RISC-V adds support for latest Andes RISC-V processor technology, including AndeStar™ V5 RISC-V Performance Extension Uppsala, Sweden—June 23,…
Intel to Adopt SiFive’s New High-Performance P550 RISC-V Cores With 7nm Platform | Paul Alcorn, Tom’s HardwareSiFive, the leading designer of chips based on the open source RISC-V architecture, announced its new SiFive Performance line of chips today that support 64-bit…