Thank You For Attending RISC-V Summit North America! | Missed the event? Watch Now.

No recent posts listed
IAR Systems extends functional safety offering for RISC-V with leading build tools for Linux | IAR Systems

IAR Build Tools for Linux for RISC-V now certified as a qualified tool for safety-related embedded development Uppsala, Sweden—October 25, 2021—IAR Systems®, the future-proof supplier…

A Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications | Marco Cococcioni, Federico Rossi, Emanuele Ruffaldi, and Saponara Sergio, IEEE Transactions on Emerging Topics in Computing

Nowadays, two groundbreaking factors are emerging in neural networks. Firstly, there is the RISC-V open instruction set architecture (ISA) that allows a seamless implementation of…

Video: Accelerating Neural Networks using RISC-V and Open Standard Software | Charles Macfarlane, Codeplay Software

Neural Networks are foundational AI constructs for recognizing relationships in data requiring processing massive datasets in the form of tensors. Tensor processing is central to…

SiFive Envisions 128-Core RISC-V SoCs as Gap With x86 and Arm Closes | Anton Shilov, Tom’s Hardware

SiFive emerged from stealth mode as a developer of small, low-power cores for microcontrollers in 2016. By late 2020, the company had a chip that…

ETH Zurich Team Unveils RISC-V-Based Snitch Processor, Boasts of Sixfold Performance Gains | Gareth Halfacree, Hackster.io

Designed with two RISC-V ISA extensions, the Snitch chip is up to 6.45 times faster than comparable processors — and more efficient, too. A team…

Research and Achievement of RISC-V for Embedded MCUs | WCH Micro Electronics

Watch the full video from WCH Micro Electronics showcasing how to create an RT-Thread project based on CH32V307.

Showcasing the key features of the RT-Thread IoT OS and toolchain! | Lance Harvie, RT-Thread IoT OS Global Tech Conference 2021

Watch the full video of how the BlueTrum AB32VG1 RISC-V based board creates a great combination. Lance Harvie presents a talk at RT-Thread IoT OS…

PUFiot -The Secure Co-processor for RISC-V | PUFsecurity Corp.

Watch the full video of PUFiot -The Secure Co-processor for RISC-V featuring English voice-over and Chinese subtitles.|

AntChain Releases First Self-developed Blockchain Security Chip, the T1 | Pandaily

At today’s Apsara Conference, AntChain, the blockchain technology arm of Ant Group, officially released the T1, its first self-developed chip. The chip is equipped with…

Vates joins RISC-V International | Vates

Vates is proud to announce joining RISC-V International as a Strategic Member. "Strategic members are organizations that are integrating RISC-V and want to have their…

We’re closing the gap with Arm and x86, claims SiFive: New RISC-V CPU core for PCs, servers, mobile incoming | Agam Shah, The Register

SiFive reckons its fastest RISC-V processor core yet is closing the gap on being a mainstream computing alternative to x86 and Arm. The yet-unnamed high-performance…

Meet Snitch: the Small and Agile RISC-V Processor | Michelle Hampson, IEEE Spectrum

Tests suggest it is six times faster than other comparable processors. As society's insatiable demand for computing power continues to grow, so too does the…

No recent posts listed
No recent posts listed
No recent posts listed
Dialog Semiconductor Selected as SiFive Preferred Power Management Partner for RISC-V Development Platforms | Dialog Semiconductor

Dialog’s highly efficient, cost effective PMICs, deliver “Exact Fit” power solutions London, United Kingdom – May 11, 2021 – Dialog Semiconductor plc (XETRA:DLG), a leading…

Standards, Open Source, And Tools | Semiconductor Engineering, Brian Bailey

EDA has been more successful creating open languages and standards rather than promoting open-source collaboration. Will this change? Read the full article.

Run Linux on BeagleV Starlight in Renode | Antmicro

BeagleV Starlight is an upcoming affordable general-purpose Linux-capable RISC-V platform, and as such understandably generates a lot of interest in the development community. It is…

Video: (EN) Accelerating RISC V AI and IoT Development with Andes Software Solutions | Andes Technology

2021 Andes RISC-V CON Webinar Date: April 28, 2021 Topic: Accelerating RISC V AI and IoT Development with Andes Software Solutions Speaker: Simon Wang, Technical…

Video: aicas and SiFive Demo on RISC-V Board

aicas and SiFive Bridge Flexibility and Performance with RISC-V, JamaicaVM Integration aicas GmbH and SiFive, Inc are enabling embedded systems developers to close the gaps…

Video: The RISC-V Online Tutor | British Computer Society Open Source Specialists

Presented Fearghal Morgan, NUI Galway, Ireland RISC-V Online Tutor provides structured, self-paced RISC-V architecture and applications training and reference. It uses the vicilogic platform (online…

Video: MPU6050 Gyro + Accelerometer Sensor Demo using VEGA Processor [ RISC-V ISA]

Demonstrating MPU6050 Gyro + Accelerometer Sensor using VEGA Microprocessor based on RISC-V ISA

Allwinner D1 RISC-V processor SDK & Documentation | JEAN-LUC AUFRANC, CNX Software

We published information about Allwinner D1 SBC and processor a few weeks ago. The news was pretty interesting as it’s the first RISC-V processor from the company,…

Linux-driven RISC-V module can plug into Raspberry Pi CM4 cluster carrier | Eric Brown, LinuxGizmos.com

Antmicro unveiled an open source, RPi CM4-compatible “ARVSOM” module that runs Linux on the RISC-V based StarFive 71×0 SoC. The ARVSOM can plug into Antmicro’s…

SiFive and Samsung Foundry Extend Partnership to Accelerate AI SoC Development

Configurable SiFive RISC-V AI SoC Development Platform is built on 14nm Samsung process technology to accelerate custom Machine Learning solutions Read the full press release.

RISC-V International Offers Academics, Individuals Free Development Boards with Up to 16GB of RAM | Gareth Halfacree, hackster.io

Early adopters, developers, and others invited to receive a free RISC-V dev board — and if you're not a member, that's free too. Read the…