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Getting Started with the ESP32-C3 RISC-V MCU | Mathias Claussen, Elektor Magazine
New release of SweRVolf RISC-V SoC project aims for lower barrier to entry | Gareth Halfacree, The Register
LoRaWAN on PineDio Stack BL604 RISC-V Board | Lup Yuen LeeEl Correo Libre Issue 42 | Gareth Halfacree, LibreCores
Synopsys Accelerates Most Stringent Functional Safety Certification of NSITEXE RISC-V Parallel Processor IP | Design and Reuse
Open Source HW and RISC-V – Linked but not the same | Luca Benini , PULP Platform
Chinese companies are interested in RISC-V to localize semiconductors | Kim Won-jung, The Korea Industry Daily
Forget Microservices: A NIC-CPU Co-Design For The Nanoservices Era | Timothy Prickett Morgan, The Next Platform
Andes Technology Corp. Brings Its Broad Family of RISC-V CPU IP to the Silicon Catalyst Semiconductor Incubator | Chip Estimate
Getting started with Bluetrum AB32VG1 RISC-V Bluetooth audio board using RT-Thread | Jean-Luc Aufranc, CNX Software
Video: CFU Playground | Alan Green, PyConline AU 2021
Why It’s the Perfect Time to Join Codasip and be Part of the RISC-V Revolution | Rupert Baines, CMO Codasip
Video: Intel to Make ARM & RISC-V Chips!!! | Gary Explains
Video: MAX30102 Pulse Oximeter and Heart Rate Sensor Demo using VEGA Processor [ RISC-V ISA]
RISC-V XIP Support Queued Ahead Of Linux 5.13 To “eXecute In Place” | Michael Larabel
Valtrix and Codasip Cooperate on Verification of RISC-V Systems
In $20bn push, Intel hopes to make US chip-making great again | Aljazeera
Verification In The Open Source Era | Brian Bailey, Semiconductor Engineering
Instructor-led course now includes hands-on labs with a RISC-V based emulated development target | Behan Webster
ESP32-C3-DevKitM-1 RISC-V WiFI & BLE board to launch for $8, modules for $1.8+ | JEAN-LUC AUFRANC (CNXSOFT)
SiFive collaborates with new Intel Foundry Services to enable innovative new RISC-V computing platforms | Sifive Blog – Patrick Little, President & CEO, SiFive
IAM949- CEO Expands and Engages Company’s Stakeholders | Podcast Interview with Calista Redmond
AndeSysC™ – A Flexible RISC-V Processor Model for SoC Virtual Prototyping | Andes Technology
Mitacs and OpenHW Group partner on $22.5M first-of-its-kind open-source research program
Getting Started with the ESP32-C3 RISC-V MCU | Mathias Claussen, Elektor MagazineThe ESP32-C3 from Espressif has been eagerly awaited. It has just one core humming away at its heart instead of the usual two cores in…
New release of SweRVolf RISC-V SoC project aims for lower barrier to entry | Gareth Halfacree, The RegisterThe SweRVolf project, a fully open system-on-chip designed as a reference platform for Western Digital's RISC-V SweRV cores, has announced a major new release promising…
LoRaWAN on PineDio Stack BL604 RISC-V Board | Lup Yuen LeeLup Yuen Lee is a hands-on IoT advisor and educator who is passionate about helping everyone create IoT products that make a difference to the…
El Correo Libre Issue 42 | Gareth Halfacree, LibreCoresRead the full newsletter, including RISC-V highlights.
Synopsys Accelerates Most Stringent Functional Safety Certification of NSITEXE RISC-V Parallel Processor IP | Design and ReuseFirst ISO 26262 ASIL D Certified RISC-V Processor with Vector Extension Tapped into Speed and Capacity of Synopsys Z01X Fault Simulation Solution Accelerating its leadership…
Open Source HW and RISC-V – Linked but not the same | Luca Benini , PULP PlatformLinked but not the same - take a look at Luca Benini's recent presentation from Visions of ECS beyond 2030 that among other things discusses the…
Chinese companies are interested in RISC-V to localize semiconductors | Kim Won-jung, The Korea Industry DailyAs global economic uncertainty and trade tensions between the United States, China and Taiwan accelerate the movement to localize the supply chain to produce and…
Forget Microservices: A NIC-CPU Co-Design For The Nanoservices Era | Timothy Prickett Morgan, The Next PlatformThe remote procedure call, or RPC, might be the single most important invention in the history of modern computing. The ability to reach out from…
Andes Technology Corp. Brings Its Broad Family of RISC-V CPU IP to the Silicon Catalyst Semiconductor Incubator | Chip EstimateAndes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced…
Getting started with Bluetrum AB32VG1 RISC-V Bluetooth audio board using RT-Thread | Jean-Luc Aufranc, CNX SoftwareBluetrum AB32VG1 is a development board based on AB5301A RISC-V microcontroller designed for Bluetooth audio applications as well as general-purpose projects that works with RT-Thread…
Video: CFU Playground | Alan Green, PyConline AU 2021The CFU-Playground allows anyone to build FPGA based accelerators for ML inferencing. With a heavy reliance on the Python based tools LiteX and nMigen, it…
Why It’s the Perfect Time to Join Codasip and be Part of the RISC-V Revolution | Rupert Baines, CMO CodasipEighteen months ago, I said: “The rise of RISC-V offers us a tremendous platform for innovation and collaboration: it has the potential to change the business model…
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Video: Intel to Make ARM & RISC-V Chips!!! | Gary Explainsntel made several major announcements recently including the launch of its Intel Foundry Services business. It will offer capacity in the U.S. and Europe, along…
Video: MAX30102 Pulse Oximeter and Heart Rate Sensor Demo using VEGA Processor [ RISC-V ISA]Demonstrating MAX30102 Pulse Oximeter and Heart Rate Sensor using VEGA Microprocessor based on RISC-V ISA Source code : https://gitlab.com/cdac-vega/
RISC-V XIP Support Queued Ahead Of Linux 5.13 To “eXecute In Place” | Michael LarabelIt looks like the Linux 5.13 kernel will be supporting an interesting RISC-V feature this spring. Queued up now in RISC-V's "for-next" branch as of this week…
Valtrix and Codasip Cooperate on Verification of RISC-V SystemsBangalore, India and Munich, Germany – March 23rd, 2021 – Valtrix Systems, the provider of design verification products for building functionally correct CPU and system-on-chip…
In $20bn push, Intel hopes to make US chip-making great again | AljazeeraIntel plans to build two factories in Arizona in challenge to Taiwanese, South Korean advanced chip-making giants. Read the full article.
Verification In The Open Source Era | Brian Bailey, Semiconductor EngineeringWhat does open-source verification mean in the context of a RISC-V processor core? Does it provide free tools, free testbenches, or the freedom to innovate?…
Instructor-led course now includes hands-on labs with a RISC-V based emulated development target | Behan WebsterWe are surrounded by electronic devices that make the modern world work. Almost all of these devices and the systems they run are “Embedded Systems”,…
ESP32-C3-DevKitM-1 RISC-V WiFI & BLE board to launch for $8, modules for $1.8+ | JEAN-LUC AUFRANC (CNXSOFT)ESP32-C3 may be one of the most expected RISC-V processors in the IoT world, as it’s eventually expected to sell for the same price as…
SiFive collaborates with new Intel Foundry Services to enable innovative new RISC-V computing platforms | Sifive Blog – Patrick Little, President & CEO, SiFiveEnabling more choice for Next-Generation Heterogeneous Compute Platforms I am excited to see Intel's new Foundry services business (IFS) in the U.S. and Europe increase…
IAM949- CEO Expands and Engages Company’s Stakeholders | Podcast Interview with Calista RedmondCalista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity…
AndeSysC™ – A Flexible RISC-V Processor Model for SoC Virtual Prototyping | Andes TechnologyAndeSysC™ is Andes virtual platform solution based on SystemC to enrich the RISC-V ecosystem. It provides extendable, flexible and near-cycle accurate models of AndesCore™ V5…
Mitacs and OpenHW Group partner on $22.5M first-of-its-kind open-source research programInitial research project awarded to CMC Microsystems, ETH Zürich, and Polytechnique Montréal will be presented on March 18 via OpenHW TV webinar. Register at https://bit.ly/3dMIay3…