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Nvidia CUDA Software Gets Ported to Open-Source RISC-V GPGPU Project | Aleksandar Kostovic , Tom’s Hardware
RISC-V Gains Traction in the Data Center | Jake Hertz, All About Circuits
All the Polynomial Multiplication You Need on RISC-V | Hwajeong Seo, Hyeokdong Kwon, Siwoo Eum, Kyungbae Jang, Hyunjun Kim, Hyunji Kim, Minjoo Sim, Gyeongju Song, and Wai-Kong Lee
Public Review Period Opens for Proposed RISC-V Scalar Cryptography Extensions | Gareth Halfacree , AB Open
RT-Thread Partnered with WCH Mircoelectronics, to Promote More Applications for RISC-V Ecosystem! | RT-Thread
Yadro’s RISC-V Designers Show Students How to Design Processors | Yuri Panchul, HabrVideo: NixOS/Nix – Cross Compilation via pkgsCross | Matthew Croughan
A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method | Zhiyu Li, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, and Zhiyi Yu, IEEE XPlore
RISC-V Chiplet Startup Raises $38m, Targets Data Center Compute | Nitin Dahad, EE TimesRNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures | Gianna Paulin, Renzo Andri, Francesco Conti, and Luca Benini, IEEE Xplore
Semiconductor veterans gather to design customizable, chiplet-based RISC-V server processors | Chris Williams, The RegisterEnd-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet? | Gianmarco Ottavi, Geethan Karunaratne, Francesco Conti, Irem Boybat, Luca Benini, and Davide Rossi
Video: Automatic end-to-end formal verification of RISC-V processors | Axiomise Formal Verification Channel
Why, and how, we’ll all be making our own computer chips in the future… | Rob Taylor
Is RISC-V China’s Semiconductor Salvation? | Tobias Mann
Enabling RISC-V Based System Development | Sandeep Nasa and Sagar Thakran, Logic Fruit Technologies
SiFive and ArchiTek Enable Secure, Private, Flexible Edge AI Computing With AiOnIc® Processor | SiFive
K210 AI Accelerator a Compact Raspberry Pi HAT for Computer Vision Applications | Saumitra Jagdale
Using TL-Verilog for FPGAs | Shivani Shah
3 RISC-V Forums Scheduled | insideHPC
Imperas’ RV32/64K Crypto Architectural Validation Test Suites Now Included in RISC-V Verification Ecosystem | Chad Cox Embedded Computing Design
DARPA pitted 500+ hackers against this computer chip. The chip won. | Gabe Cherry Michigan Engineering
Ron Black Joins Codasip as Executive Chairman
An Insider’s View Of Verifying Custom RISC-V Processor Cores | Shubhodeep Roy Chodhury, Semiconductor Engineering
Nvidia CUDA Software Gets Ported to Open-Source RISC-V GPGPU Project | Aleksandar Kostovic , Tom’s HardwareRISC-V has been one of the hottest topics in the world of computing, as the Instruction Set Architecture (ISA) allows for extensive customization and is…
RISC-V Gains Traction in the Data Center | Jake Hertz, All About CircuitsRISC-V is often associated with embedded projects. Now, the open-source ISA may be a more common player in higher-end computing markets. Founded in a UC…
All the Polynomial Multiplication You Need on RISC-V | Hwajeong Seo, Hyeokdong Kwon, Siwoo Eum, Kyungbae Jang, Hyunjun Kim, Hyunji Kim, Minjoo Sim, Gyeongju Song, and Wai-Kong LeeRead the full paper. Abstract: Polynomial multiplication is a core operation for public key cryptography, such as pre-quantum cryptography (e.g. elliptic curve cryptography) and post-quantum…
Public Review Period Opens for Proposed RISC-V Scalar Cryptography Extensions | Gareth Halfacree , AB OpenThe RISC-V Cryptography Extensions Task Group has opened a public review period on a raft of instruction set extensions, ahead of their planned adoption as…
RT-Thread Partnered with WCH Mircoelectronics, to Promote More Applications for RISC-V Ecosystem! | RT-ThreadRT-Thread has entered into a partnership with WCH Microelectronics to promote more applications in the RISC-V ecosystem. WCH is known in the chip industry for…
Yadro’s RISC-V Designers Show Students How to Design Processors | Yuri Panchul, HabrIn a week there will be an exhibition, ChipEXPO, at which there will be an iron design school for beginners with exercises on FPGA boards,…
Video: NixOS/Nix – Cross Compilation via pkgsCross | Matthew CroughanWatch Matthew Croughan give an introduction to using the Nix CLI to cross-compile packages for other architectures. If you are struggling to enable Flakes, you…
A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method | Zhiyu Li, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, and Zhiyi Yu, IEEE XPloreOver the past decade, the design of low-power processors is a primary requirement of emerging applications, as Internet of Things (IoT) and neuromorphic chips. Therefore,…
RISC-V Chiplet Startup Raises $38m, Targets Data Center Compute | Nitin Dahad, EE TimesVentana Micro Systems, a RISC-V startup headquartered in Cupertino, CA, has emerged from stealth announcing $38 million in funding and revealing details of its multi-core…
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures | Gianna Paulin, Renzo Andri, Francesco Conti, and Luca Benini, IEEE XploreRadio resource management (RRM) is critical in 5G mobile communications due to its ubiquity on every radio device and its low latency constraints. The rapidly…
Semiconductor veterans gather to design customizable, chiplet-based RISC-V server processors | Chris Williams, The RegisterA Silicon Valley startup is stepping out of stealth mode today, publicly vowing to supply high-performance data-center-class RISC-V processors. Ventana Micro Systems said since its…
End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet? | Gianmarco Ottavi, Geethan Karunaratne, Francesco Conti, Irem Boybat, Luca Benini, and Davide RossiIn-Memory Acceleration (IMA) promises major efficiency improvements in deep neural network (DNN) inference, but challenges remain in the integration of IMA within a digital system.…
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Video: Automatic end-to-end formal verification of RISC-V processors | Axiomise Formal Verification ChannelProcessor verification has always been a significant challenge. With the open-source RISC-V® ISA, we see an emerging revolution for processor design with lots of new…
Why, and how, we’ll all be making our own computer chips in the future… | Rob TaylorIf you read the tech news, it can’t have slipped your attention that significant changes are a foot in the computer chip industry. New chief…
Is RISC-V China’s Semiconductor Salvation? | Tobias MannU.S. trade restrictions and growing pressure from the Chinese Communist Party to end reliance on foreign chipmakers has left many Chinese technology companies understandably worried. Over the…
Enabling RISC-V Based System Development | Sandeep Nasa and Sagar Thakran, Logic Fruit TechnologiesVerifying a RISC-V Core-Based Design: A Primer This article focuses on providing a jump start on RISC-V development. It shows how to build a verification…
SiFive and ArchiTek Enable Secure, Private, Flexible Edge AI Computing With AiOnIc® Processor | SiFiveNew Edge AI processor accelerates key workloads while offering flexibility for changing AI needs SAN MATEO, Calif. – March 18, 2021 – SiFive, Inc., the…
K210 AI Accelerator a Compact Raspberry Pi HAT for Computer Vision Applications | Saumitra JagdaleXaLogics’s AI Accelerator with K210 SoC comes with a dual-core RISC-V AI processor featuring low power consumption than its competing Coral USB Accelerator, and Intel…
Using TL-Verilog for FPGAs | Shivani ShahA few months back, I came across a workshop titled ‘RISC-V based Microprocessor for You in Thirty Hours (MYTH)’, that was about designing RISC-V core…
3 RISC-V Forums Scheduled | insideHPCThe RISC-V Forum will hold three conferences starting next month that are free of charge to members and non-members and designed to provide deep-dive technical content…
Imperas’ RV32/64K Crypto Architectural Validation Test Suites Now Included in RISC-V Verification Ecosystem | Chad Cox Embedded Computing DesignImperas Software released its latest update to the RISC-V architectural validation test suites for the RV32/64K Crypto (scalar) extension. The released tests support the RISC-V ISA…
DARPA pitted 500+ hackers against this computer chip. The chip won. | Gabe Cherry Michigan EngineeringUniversity of Michigan’s MORPHEUS technology emerges unscathed from bug bounty effort.| Medium Read An “unhackable” computer chip lived up to its name in its first bug…
Ron Black Joins Codasip as Executive ChairmanMunich, Germany – March 16th, 2021 – Codasip, the leading supplier of customizable RISC‑V processor IP, announced that semiconductor industry veteran Dr Ron Black has joined…
An Insider’s View Of Verifying Custom RISC-V Processor Cores | Shubhodeep Roy Chodhury, Semiconductor EngineeringThis article is derived from a talk at the RISC-V Summit in December 2020 that Bill McSpadden, principal verification engineer at Seagate Technology, gave on the…