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RISC-V Becoming Less Risky With The Right Verification | Rob Van Blommestein, Semiconductor Engineering

RISC-V continues to make headlines across the electronic design industry. You may have seen the recent news that the OpenHW Group is delivering their first…

Embedded Trends and Tech to Watch in 2021 | Shawn Prestridge, Electronic Design

2021 will be a breakout year for RISC-V. We’ve seen R&D groups at large customers dabble with RISC-V to see if they want to base…

Android 10 ported to RISC-V board powered by Alibaba T-Head XuanTie C910 Processor | Jean-Luc Aufranc, CNX Software

RISC-V has made a lot of progress in just a few years, but for anything requiring 3D graphics acceleration, it’s not quite there yet. and we…

Overview of Diplomacy for writing effective hardware design language Chisel (Japanese)

ハードウェア記述言語Chiselをもっともっと活用するためのDiplomacy概説 発表者:msyksphinz (FPGA開発日記著者) @msyksphinz_dev https://msyksphinz.hatenablog.com Chisel使ってますか? Scalaをベースとしたハードウェア構築言語. 高位合成言語ではない SiFiveのRISC-V IPで採用されている Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom Chiselの基礎 : 「Chiselを始めたい人に読んで欲しい本」 https://nextpublishing.jp/book/12162.html ChiselがVerilogを生成するまで ChiselはScalaのDSLなので、Chisel CompilerはScalaで記述してある Chisel CompilerはFIR (Flexible Interpretation Representation)と呼ばれる中間言語を生成する…

The Android system on RISC-V has come!| Open Chip Community

The Android system on RISC-V has come! T-Head has ported Android 10 on RISC-V architecture. Android's primary purpose is to create an open software platform…

Android 10 ported to homegrown multi-core RISC-V system-on-chip by Alibaba biz, source code released | Matthew Hughes, The Register

Alibaba-owned T-Head Semiconductor says it has ported Android 10 to its own RISC-V chips, highlighting increased momentum for the open-source instruction set architecture (ISA) against…

Antmicro Joins the EC’s VEDLIoT Project to Bring Ultra-Efficient RISC-V Deep Learning to the IoT | Gareth Halfacree, hackster.io

Open source silicon pioneer Antmicro has announced its involvement in the European Commission's Very Efficient Deep Learning in Internet of Things (VEDLIoT) project, with the…

RISC-V CPU Performance | Maven Silicon

This video explains how Maven Silicon measures the CPU performance and how we try to improve the processor performance by improving its clock frequency and…

The Future Is Now: Mark Himelstein of RISC-V On How Their Technological Innovation Will Shake Up The Tech Scene | Fotis Georgiadis, Authority Magazine

Some of the greatest “rocket science” in RISC-V is the simplicity, elegance, and flexibility of it. While some of the individual pieces are not “rocket…

Formal Bytes, Episode 39: Abstraction in 7 minutes! | Axiomise Formal Verification Channel

We demystify abstraction in today's podcast. Abstraction is the cornerstone of modern-day scalable formal verification. Classic papers in formal literature talk about abstraction as a…

SiFive Helping To Teach Kids Programming With RISC-V HiFive Inventor Coding Kit | Michael Larabel, Phoronix

SiFive in cooperation with Tynker and BBC Learning have launched a Doctor Who themed HiFive Inventor Coding Kit. This Initial HiFive Inventor Coding Kit is…

Open Hardware: Open Source conquering processors (French) | David Feugey, Silicon.fr

Au début des années 2000, une communauté d’ingénieurs veut allier électronique et Open Source. Leur idée : proposer des plans de cartes mères, de composants…

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