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First Xuantie Partner Conference in China Highlights Growth Momentum of Thriving RISC-V Community

The first Xuantie Partner Conference, organized by Alibaba Group’s chip development business, T-Head, took place in Shanghai, China last week. It marks another major milestone…

What to see at Embedded World 2023

RISC-V is leading the inevitable era of open computing at Embedded World 2023 in Nuremberg from March 14-16, as we bring the community together to…

RISC-V Webinar with Andes and Imperas: “RISC-V Design Innovations with Custom Extensions.”

On Thursday, Feb. 23rd, Andes and Imperas held a webinar on "RISC-V Design Innovations with Custom Extensions." At the end of the formal remarks, the…

RISC-V Newsletter – March 2, 2023

RISC-V Momentum  We’re off to an incredible start in 2023! We have already ratified several extensions and are on course to complete six ratifications in…

First-ever RISC-V Summit Europe Will Demonstrate Technical and Commercial Momentum Across Industries

The Barcelona RISC-V Summit from June 5-9 to focus on industries such as Automotive, High Performance Compute/Data Center, and Security; Call for Submissions and Sponsorships…

Maven Silicon’s RISC-V Processor IP Verification Flow

Author: P R Sivakumar, Founder and CEO, Maven Silicon LinkedIn Profile: https://www.linkedin.com/in/sivapr/   1.Introduction RISC-V is a general-purpose license-free open Instruction Set Architecture with multiple…

Porting NuttX Real-Time Operating System on PolarFire® SoC FPGA

NuttX Operating System NuttX is free open-source RTOS that focuses on standards compliance and small footprint. A basic version of NuttX can be run on…

Announcing The First International Workshop for HPC based on RISC-V

RISC-V has seen phenomenal growth in recent years across a range of applications. One of the most exciting areas of development is High Performance Computing…

XuanTie Matrix Multiply Extension Instructions

Author: Qiu Jing The rise of AI has increased the demand for computing power by orders of magnitude. To meet the needs of AI for…

TEE SoC Based on RISC-V

Yuehai Chen, Huarun Chen, Shaozhen Chen Guangdong University of Technology In the China Postgraduate IC Innovation Competition this August, T-Head sponsored the design challenge: Building…

CPU RTL co-simulation in Renode

Support for co-simulating HDL models in Renode with Verilator has been an integral part of the framework since the 1.7.1 release, introducing a new dimension of…

Xuantie RISC-V TEE solution for MCU

Author: Lijie Mao 1. Overview TEE (Trusted Execution Enviroment) has been the most widely used method for device security protection. In this article, we will…

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Alibaba Cloud
Xuantie IOMMU from T-Head for RISC-V | Chong Ren, Alibaba Cloud

The recent development of the RISC-V IOMMU effort has attracted substantial attention from the RISC-V community. Xuantie IOMMU from T-Head Semiconductors of Alibaba Group, holding…

Mi-V Ecosystem Partner Solutions | Leah Iris, Microchip

The Mi-V RISC-V ecosystem is a continuously expanding, comprehensive suite of tools and design resources developed by Microchip and numerous third parties to fully support…

Alibaba Cloud
XuanTie VirtualZone: RISC-V-based Security Extensions | Xuan Jian, Alibaba Cloud

Introduction Among many new things in the 21st century, internet and IoT have been one of the most significant human advancements. As fast-paced and accelerating…

RISC-V RV32I JALR Instruction | Maven Silicon

This video explains the RV32I JALR instruction. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats,…

FOSSi Explosion 2021 | Olof Kindgren, FOSSi Foundation and Qamcom

Do you know what just happened? 2021 just happened. Most years has its ups and downs, but when it comes to 2021 it seems like…

Intel Corporation Makes Deep Investment in RISC-V Community to Accelerate Innovation in Open Computing

RISC-V welcomes Intel to the Board of Directors to collaborate on RISC-V IP and contribute engineering expertise to accelerate RISC-V software development ZURICH – February…

RISC-V RV32I J-Type | Maven Silicon

This video explains the RV32I J-Type instructions.  RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats,…

Semico Research’s New Report Predicts There Will Be 25 Billion RISC-V-Based AI SoCs By 2027 | Rich Wawrzyniak, Semico Research Corporation

Research underscores current RISC-V architecture momentum, emphasizing impressive growth in consumer, enterprise and communication markets   RISC-V is leading the open era of computing across…

Open source FPGA platform for Rowhammer security testing in the data center | Antmicro

Our work together with Google and the world’s research community on detecting and mitigating the Rowhammer problem in DRAM memories has been proving that the…

Alibaba Cloud
Alibaba Cloud Opens Up IoT Technology Development Platform | Wang Cindy, Alibaba Cloud

Alibaba Cloud, the digital technology and intelligence backbone of Alibaba Group, announced it has opened the source code of Yun on Chip (YoC), its proprietary…

RISC-V RV32I S-Type | Maven Silicon

This video explains the RV32I S-Type instructions.  RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats,…

Edge AI on Low-Footprint RISC-V | Alexander Stanitzki, Fraunhofer IMS

The integration of AI algorithms on end devices (“Edge AI”, “AI of Things”, TinyML,..)  is conquering the domain of resource constrained microcontrollers and cost-efficient ASIC…

Alibaba Cloud
Xuantie IOMMU from T-Head for RISC-V | Chong Ren, Alibaba Cloud

The recent development of the RISC-V IOMMU effort has attracted substantial attention from the RISC-V community. Xuantie IOMMU from T-Head Semiconductors of Alibaba Group, holding…

Mi-V Ecosystem Partner Solutions | Leah Iris, Microchip

The Mi-V RISC-V ecosystem is a continuously expanding, comprehensive suite of tools and design resources developed by Microchip and numerous third parties to fully support…

Alibaba Cloud
XuanTie VirtualZone: RISC-V-based Security Extensions | Xuan Jian, Alibaba Cloud

Introduction Among many new things in the 21st century, internet and IoT have been one of the most significant human advancements. As fast-paced and accelerating…

RISC-V RV32I JALR Instruction | Maven Silicon

This video explains the RV32I JALR instruction. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats,…

FOSSi Explosion 2021 | Olof Kindgren, FOSSi Foundation and Qamcom

Do you know what just happened? 2021 just happened. Most years has its ups and downs, but when it comes to 2021 it seems like…

Intel Corporation Makes Deep Investment in RISC-V Community to Accelerate Innovation in Open Computing

RISC-V welcomes Intel to the Board of Directors to collaborate on RISC-V IP and contribute engineering expertise to accelerate RISC-V software development ZURICH – February…

RISC-V RV32I J-Type | Maven Silicon

This video explains the RV32I J-Type instructions.  RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats,…

Semico Research’s New Report Predicts There Will Be 25 Billion RISC-V-Based AI SoCs By 2027 | Rich Wawrzyniak, Semico Research Corporation

Research underscores current RISC-V architecture momentum, emphasizing impressive growth in consumer, enterprise and communication markets   RISC-V is leading the open era of computing across…

Open source FPGA platform for Rowhammer security testing in the data center | Antmicro

Our work together with Google and the world’s research community on detecting and mitigating the Rowhammer problem in DRAM memories has been proving that the…

Alibaba Cloud
Alibaba Cloud Opens Up IoT Technology Development Platform | Wang Cindy, Alibaba Cloud

Alibaba Cloud, the digital technology and intelligence backbone of Alibaba Group, announced it has opened the source code of Yun on Chip (YoC), its proprietary…

RISC-V RV32I S-Type | Maven Silicon

This video explains the RV32I S-Type instructions.  RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats,…

Edge AI on Low-Footprint RISC-V | Alexander Stanitzki, Fraunhofer IMS

The integration of AI algorithms on end devices (“Edge AI”, “AI of Things”, TinyML,..)  is conquering the domain of resource constrained microcontrollers and cost-efficient ASIC…