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In the Media
RISC-V Community News | Dec 17, 2019
RISC-V Based PolarFire SoC FPGA And Devkit Coming In Q3 2020 | Jean-Luc Aufranc, CNX Software

Reports
Jeffrey Osier-Mixon | Dec 17, 2019
Getting Started with RISC-V Europe Roadshow Proceedings

In the Media
RISC-V Community News | Dec 17, 2019
RISC-V Grows Globally As An Alternative To Arm And Its License Fees | Dean Takahashi, VentureBeat

In the Media
RISC-V Community News | Dec 17, 2019
RISC-V Xmas Gifts: SiFive Emits Vector-Enabled Cores, Western Digital Teases New SweRVs, VxWorks Hugs ISA, Samsung Rolls It Into 5G | Chris Williams, The Register

In the Media
RISC-V Community News | Dec 17, 2019
Microchip Announces First RISC-V-Based SoC FPGA To Use Half The Power Of Other FPGAs | Lisa Boneta, All About Circuits

In the Media
RISC-V Community News | Dec 17, 2019
SiFive Learn Inventor Is A Wireless RISC-V Development Kit Inspired By BBC Micro:bit | Jean-Luc Aufranc, CNX Software

In the Media
RISC-V Community News | Dec 17, 2019
Codasip Partners With Western Digital On Open‑Source Processors | Julien Happich, eeNews Europe

In the Media
RISC-V Community News | Dec 17, 2019
Andes’ Core Has RISC-V Vector Instruction Extension | Nitin Dahad, EE Times

In the Media
RISC-V Community News | Dec 16, 2019
Greenwaves Preps GAP9 IoT Processor On FDSOI | Peter Clarke, eeNews Europe

In the Media
RISC-V Community News | Dec 16, 2019
Aerendir Mobile Inc. And SiFive Inc. Collaborate To Accelerate The Adoption Of AI-Enabled Processors | Tiera Oliver, Embedded Computing Design

News
Jeffrey Osier-Mixon | Dec 12, 2019
Curated List of RISC-V Education Materials Now Available

In the Media
RISC-V Community News | Dec 11, 2019
Cobham Releases RISC-V Processor IP Core

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