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What is RISC-V?
Integrating Tile Link UH in the Caravan Framework: A Journey of Enhanced Functionality
RISC-V rises to software ecosystem challenge
DFRobot Launches the All-In-One UNIHIKER, a Single-Board Arm Computer with Display and RISC-V MCUMilk-V Unveils Its Third RISC-V Board in a Month: The $9 Dual-Core Linux-Capable Milk-V Duo
RISC-V gathers pace in EuropeStartup plans customizable RISC-V edge AI speech processor | Nick Flaherty, EE News EuropeImagination, GHS team for RTOS and tools on RISC-V CPUs | Nick Flaherty, EENews Europe
Agile Analog launches first complete RISC-V analog IP subsystem at RISC-V Summit Europe
Interview with Calista Redmond – RISC-V summit Barcelona
Configurable 64-bit RISC-V IP Targets Machine Learning, Other Advanced Apps | Alix Paultre, Electronic DesignComputing at the Ultimate Edge – Space | Wisse Hettinga, EENews Europe
Sipeed Teases a RISC-V System-on-Module That “Beats the Raspberry Pi 4” in Performance | Gareth Halfacree, Hackster.io
Imagination extends its commitment to RISC-V with an upgrade to Premier level membership
Siemens pioneers commercial grade Linux support for the RISC-V architecture
RISC-V SBC VisionFive 2 Officially Shipped
CHIPS Alliance Welcomes the Caliptra Open Source Root of Trust Project
Examining the Top Five Fallacies About RISC-V
Ventana Introduces Veyron, World’s First Data Center Class RISC-V CPU Product Family
Ashling announce availability of their new Vitra-XS Debug & Trace Probe
XMOS Announces Software-defined SoC Platform Now Compatible with RISC-V
Codasip Launches SecuRISC5 initiative
Imperas releases new updates, test suites, and functional coverage library to support the rapid growth in RISC-V Verification
Microchip Showcases RISC-V-Based FPGA and Space-Compute Solutions at RISC-V Summit
What is RISC-V?Even for computing hobbyists, RISC-V is a bit in the weeds, but perhaps not for long. It's one of the rising stars in the computing…
Integrating Tile Link UH in the Caravan Framework: A Journey of Enhanced FunctionalityWe are thrilled to share the details of our recent project, where we successfully integrated Tile Link UH (Ultra High) into the Caravan framework. Tile…
RISC-V rises to software ecosystem challengeRISC-V, the open standard instruction set architecture (ISA) alternative to Intel and ARM, held its first European summit on 5 to 9 June 2023 in…
DFRobot Launches the All-In-One UNIHIKER, a Single-Board Arm Computer with Display and RISC-V MCUDFRobot has announced the launch of a new all-in-one single board computer (SBC) development platform, designed for plug-and-play programming and bringing its own 2.8" touchscreen…
Milk-V Unveils Its Third RISC-V Board in a Month: The $9 Dual-Core Linux-Capable Milk-V DuoRISC-V startup Milk-V has announced yet another development board built around the free and open source instruction set, this time a compact development device clearly…
RISC-V gathers pace in EuropeThe RISC-V Summit Europe brought together developers, architects, technical decision and policy makers from across European RISC-V ecosystem for the first time in the region…
Startup plans customizable RISC-V edge AI speech processor | Nick Flaherty, EE News EuropeAONDevices has developed an efficient edge AI denoising technology for applications that require minimal power and latency running on its forthcoming accelerator IP and hardware…
Imagination, GHS team for RTOS and tools on RISC-V CPUs | Nick Flaherty, EENews EuropeGreen Hills Software has ported its µ-velOSity safety- and security-certified real-time operating system (RTOS) to the real time RISC-V cores developed by Imagination Technologies, with…
Agile Analog launches first complete RISC-V analog IP subsystem at RISC-V Summit EuropeAgile Analog, the customisable analog IP company, is launching the first complete analog IP subsystem for RISC-V applications at the RISC-V Summit Europe in Barcelona…
Interview with Calista Redmond – RISC-V summit BarcelonaAt the RISC-V summit in Barcelona eeNews is meeting up with Calista Redmond. She is the CEO of RISC-V International. In our conversation we are…
Configurable 64-bit RISC-V IP Targets Machine Learning, Other Advanced Apps | Alix Paultre, Electronic DesignConfigurable high-bandwidth RISC-V cores with vector units can be made to directly address challenging applications like machine learning, AI, and other cutting-edge spaces. Semidynamics is a…
Computing at the Ultimate Edge – Space | Wisse Hettinga, EENews EuropeeeNews Europe is meeting up with Gerard Rauwerda, Business Developer with Technolution. We discuss the RISC-V developments over the years and the role Technolution played,…
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Sipeed Teases a RISC-V System-on-Module That “Beats the Raspberry Pi 4” in Performance | Gareth Halfacree, Hackster.ioWith four RISC-V cores running at 2.5GHz and up to 16GB of RAM, the compact Lichee Module 4 A aims to outperform Raspberry Pi's best…
Imagination extends its commitment to RISC-V with an upgrade to Premier level membershipLondon, England – 14th December 2022 – Imagination Technologies announces it has upgraded to the Premier RISC-V International membership level, further establishing its commitment to drive growth for the RISC-V ecosystem.…
Siemens pioneers commercial grade Linux support for the RISC-V architecturePLANO, TEXAS, December 12, 2022 - Siemens Digital Industries Software today announced that its Sokol™ Flex OS software now supports RISC-V embedded development with the…
RISC-V SBC VisionFive 2 Officially ShippedDecember 14, 2022 - Recently, StarFive Technology has completed production and testing of the first batch of VisionFive 2 SBCs, which has started shipment and…
CHIPS Alliance Welcomes the Caliptra Open Source Root of Trust ProjectSAN FRANCISCO, December 13, 2022 – CHIPS Alliance, a Linux Foundation project and leading consortium advancing common and open hardware for interfaces, processors and systems, announced…
Examining the Top Five Fallacies About RISC-VIn a little over a decade, RISC-V has arguably become at least the third most important instruction set architecture (ISA) for future applications of computing.…
Ventana Introduces Veyron, World’s First Data Center Class RISC-V CPU Product FamilyCUPERTINO, Calif. – December 13, 2022 – Ventana Micro Systems Inc. today announced its Veyron family of high performance RISC-V processors. The Veyron V1 is…
Ashling announce availability of their new Vitra-XS Debug & Trace ProbeDec-12, 2022 RISC-V Summit, San Jose, Silicon Valley, California, USA - Today Ashling announced availability of Vitra-XS their newest member of the Ashling probe family.…
XMOS Announces Software-defined SoC Platform Now Compatible with RISC-VBristol, UK – December, 12 2022 – XMOS today reveals a RISC-V compatible architecture for the fourth generation of its xcore platform. The collaboration delivers the…
Codasip Launches SecuRISC5 initiativeMunich, Germany – December 12, 2022 – Codasip, the leader in processor design automation and RISC-V processor IP, today launched SecuRISC5, a Codasip initiative to…
Imperas releases new updates, test suites, and functional coverage library to support the rapid growth in RISC-V VerificationOxford, United Kingdom – December 12th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates to ImperasDV to support the…
Microchip Showcases RISC-V-Based FPGA and Space-Compute Solutions at RISC-V SummitCHANDLER, Ariz. – December 8, 2022 – Mid-range FPGAs and System-on-Chip (SoC) FPGAs have played a major role in moving computer workloads to the network edge.…