If the recent RISC-V Summit proved one thing it’s that open-source hardware design, and particularly the RISC-V instruction set architecture (ISA) has entered the mainstream. It is a design methodology and architecture to watch closely. Across a broad range of applications from data center, to automotive, to IoT, RISC-V processors are finding a fit to address the huge processing demands of embedded AI. As is the case with any complex system design, a primary care-about is a robust design that is bug-free. Given the complexity of these designs, getting a new RISC-V implementation to that fully verified state can be a daunting task. An effective approach to this problem is by deploying formal verification. Using this approach can be challenging due to the expertise needed but this is where Axiomise can help. The company’s mission to “make formal normal” and its approach, along with RISC-V specific enhancements was on display at the Summit. Read on to see how Axiomise accelerates RISC-V designs with next generation formalISA®.
