At the 2025 RISC-V Summit in China, Nvidia announced that its CUDA software platform will be made compatible with the RISC-V instruction set architecture (ISA) on the CPU side of…
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MALTA, N.Y. and SAN JOSE, Calif., July 08, 2025 (GLOBE NEWSWIRE) -- GlobalFoundries (Nasdaq: GFS) (GF) today announced a definitive agreement to acquire MIPS, a leading supplier of AI and…
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Qualifying an AI-class RISC-V SoC demands proving that wide vectors, deep caches, and high-speed I/O operate flawlessly long before tape-out. At the recent Andes RISC-V Conference, Andes Technology and S2C…
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San Jose, CA & Hyderabad, India- June 12, 2025: Cyient Semiconductors Private Limited, a fast-growing custom silicon company based in Hyderabad, and MIPS, a global leader in RISC-V processor IP, today…
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Today’s system-on-chip (SoC) designs integrate unprecedented numbers of diverse IP cores, from general-purpose CPUs to specialized hardware accelerators, including neural processing units (NPUs), tensor processors, and data processing units (DPUs).…
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In just two years, Semidynamics has “evolved from RISC-V with AI to AI with RISC-V”, Semidynamics’ chief sales officer Volker Politz said at this week’s RISC Summit Europe 2025 in…
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Flow Computing in Finland has started alpha testing of a RISC-V compiler for its Parallel Processing Unit (PPU) AI block. The PPU is capable of increasing any CPU architecture by up…
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Laguna Hills, California. BrainChip Holdings Ltd released information it is now integrating Andes Technology’s RISC-V cores with its NPUs. According to the press release, the companies will exhibit BrainChip’s Akida AKD1500 on Andes’ QiLai…
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Laguna Hills, California. BrainChip Holdings Ltd released information it is now integrating Andes Technology’s RISC-V cores with its NPUs. According to the press release, the companies will exhibit BrainChip’s Akida AKD1500 on Andes’ QiLai…
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Semidynamics has introduced Cervell™, a highly scalable and fully programmable Neural Processing Unit (NPU) architected on RISC-V. Cervell seamlessly merges CPU, vector, and tensor capabilities within a unified, all-in-one architecture, enabling…
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