Developed with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting next-gen wearables, drones, and IoT sensors. In a move aimed at the growing...
Google Research has open-sourced its Coral NPU IP (previously codenamed Kelvin), which it is giving to the industry in a bid to accelerate edge AI implementations by reducing fragmentation and...
Annual RISC-V Summits, organized by RISC-V International, serve as vital hubs for innovation, writes SemiWiki's Daniel Nenni.
At RISC-V North American Summit in Santa Clara, Ashling and Embecosm today announced robust ExecuTorch implementations optimised for resource-constrained devices, including RISC-V based microcontrollers. The collaboration enables developers to deploy...
By running an open-source NVIDIA Deep Learning Accelerator directly on a RISC-V chip (without a traditional operating system), a group of researchers has achieved impressive performance and energy efficiency.
EMASS has introduced the ECS-DoT, a 22nm microprocessor designed to bring milliWatt-scale intelligence directly to edge and IoT devices.
SiFive just announced an array of new additions to its product stack that run the gamut, from tiny, ultra lower-power designs for far edge IoT devices, to more powerful engines...
We explore how companies across industries are proving the viability of RISC-V as a native architecture for modern AI workloads
by Ashley Stevens, Director of Product Management and Marketing at Arteris The amount of compute used to train frontier AI models has been doubling roughly every five to six months, but...
