Join Andes Technology on October 7 for an in-person technical workshop at SEMI Headquarters in Milpitas, CA. Explore practical ways to improve RISC-V processor performance through custom instructions, strategies for…
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'V Questions with…' uncovers the backstory to a RISC-V member's latest work in 5 questions. Here, I talk to the duo behind BER10, the sovereign SoC that Barcelona's Openchip taped…
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Project Snapshot This blog post reports on the experiences and roadmap of the RISER project, which since January 2023 has been developing first-generation all-European RISC-V cloud server and accelerator prototypes…
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RISC-V Summit North America 2025 will bring the global RISC-V community together in Santa Clara for two days of keynotes, technical sessions, workshops, and demos.
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Rivos and Canonical have partnered to enhance RISC-V-readiness in Ubuntu for Data Centers, creating a streamlined and optimized Linux experience, specifically designed for Rivos platforms. This collaboration marks a significant…
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This blog looks at the benefit of Rivos and Canonical partnering and how this partnership will impact future AI and Data Analytics use cases. Artificial intelligence is transforming business operations…
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RISC-V, an open standard instruction set architecture (ISA), is rapidly shaping the future of high-performance computing, edge computing, and artificial intelligence. The RISC-V customizable and scalable ISA enables a new…
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CUPERTINO, Calif. – November 7, 2023 – Ventana Micro Systems Inc. today announced the second generation of its Veyron family of RISC-V processors. The new Veyron V2 is the highest performance RISC-V…
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CUPERTINO, Calif. – December 13, 2022 – Ventana Micro Systems Inc. today announced its Veyron family of high performance RISC-V processors. The Veyron V1 is the first member of the…
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Company hopes to match or even exceed x86 and Arm performance for data center infrastructure and applications. The data center is becoming more heterogeneous in terms of customized processors, accelerating…
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