EEWorldOnline: MIPS releases multithreaded processor for edge computing
EEWorldOnline: MIPS has begun sampling its new I8500 processor, a scalable, multithreaded data movement processor IP designed for real-time, event-driven computing... Read more.
RISC-V International Names Tom Gall as Vice President of Technology
Open-technology veteran Gall will drive RISC-V International’s technical vision and collaboration strategy, strengthening the organisation’s push for worldwide... Read more.
EDN: The next RISC-V processor frontier: AI
EDN: At RISC-V Summit North America 2025, industry leaders unveiled the latest advances in CPU cores, vector processors, and AI-powered designs shaping the next... Read more.
All About Circuits: Upbeat Technology’s RISC-V MCU Takes Flight With Near-Threshold Computing
Developed with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting next-gen wearables, drones, and IoT sensors.... Read more.
EETimes: Google Open-Sources NPU IP, Synaptics Implements It
Google Research has open-sourced its Coral NPU IP (previously codenamed Kelvin), which it is giving to the industry in a bid to accelerate edge AI implementations... Read more.
SemiWiki: Insights from the 2025 RISC-V Summits and Andes Technology’s Pivotal Role
Annual RISC-V Summits, organized by RISC-V International, serve as vital hubs for innovation, writes SemiWiki's Daniel Nenni.... Read more.
NewElectronics: RISC-V International to Announce 25% Market Penetration
RISC-V International is set to announce that silicon on the open-standard has reached 25% market penetration, according to research from SHD Group whose findings... Read more.
Ashling and Embecosm Extend PyTorch AI to RISC-V Embedded Devices
At RISC-V North American Summit in Santa Clara, Ashling and Embecosm today announced robust ExecuTorch implementations optimised for resource-constrained devices,... Read more.
Optimizing Hardware for Neural Network Inference using Virtual Prototypes
Project Snapshot
Identifying the optimal hardware configuration for running NN inference on edge devices is critical for maximizing performance. Tailoring HW designs... Read more.
A RISC-V Based Accelerator for Post Quantum Cryptography
Project Snapshot
Post-Quantum Cryptography (PQC) is a topic of increased interest in the past decade, both with regards to the cryptosystem definition and the hardware... Read more.