PLS Programmierbare Logik & Systeme in Germany has added support for the RISC-V open instruction set architecture to test and debug Infineon’s latest automotive processor design.
The latest PLS Universal Debug Engine (UDE) 2025 is being used to simplify trace-based system analysis and debugging a prototype of the next generation Aurix microcontroller.
This Automotive RISC-V Prototype consists of a RISC-V Core Virtual Prototype (VP) based on the Synopsys Virtual Development Kit (VDK). It is bundled with software drivers and a template project for rapid prototyping to form a Software Development Kit (SDK) that enables pre-silicon software development. The VDK models the complete MCU including the RISC-V-based multi-core cluster, the interrupt controller, the interprocessor communication and the proven automotive peripherals.
