It’s been a year of change so far for the RISC-V movement, from new leadership to an outpouring of hardware.
In fifteen years, RISC-V has gone from an academic project at UC Berkeley to one of the major technological trends in compute. The ISA has since flourished in an era that appreciates its royalty-free, open-source building blocks.
RISC-V’s modular approach allows anyone, anywhere, to benefit from IP contributed and produced by RISC-V. Image used courtesy of Siemens
In recent weeks, RISC-V has celebrated several notable wins, from major organizational announcements to new RISC-V-based technologies hitting the market.
RISC-V’s 15-Year Anniversary
In honor of RISC-V’s recent 15-year anniversary, SiFive published a brief history and optimistic forecast on the future of the ISA.
In 2010, RISC-V was born from the Parallel Computing Laboratory (Par Lab) at UC Berkeley. At the time, the ISA presented a new approach that avoided legacy instruction complexity to achieve modular scalability. Over time, the architecture’s open nature drove broad adoption, now present in billions of devices and backed by more than 4,500 members in 70 countries.
SiFive itself was founded by RISC-V’s creators and has translated this architecture into commercially viable IP cores ranging from minimal embedded controllers to high-performance vector processors. To date, its technology stack has shipped in over two billion devices and includes proprietary contributions like WorldGuard and vector-matrix extensions.
As proprietary ISAs raise concerns over vendor lock-in, SiFive anticipates that industry leaders will increasingly rely on RISC-V to decouple hardware design from legacy constraints and to enable full-stack hardware customization.