World RISC-V Days – Graz Austria
February 24 @ 2:00 pm - 5:00 pm
Join the World RISC-V Days – Graz Edition, an in-person event encouraging RISC-V community collaboration. This gathering invites students, educators, developers, and industry leaders for discussions and keynotes to explore and connect with emerging RISC-V communities worldwide.
Preliminary Program:
- 14:00 Introduction
- 14:10 – 15:30 Pitch Talks
- 15:30 – 17:00 Poster/Showcase Session and Networking
Confirmed speakers:
- Maja Malenko (CHERI Ambassador; Insights on current CHERI developments)
- Leo Moser (Greyhound: A Reconfigurable and Extensible RISC-V SoC and eFPGA on IHP SG13G2)
- Prof. Marcel Baunach (RISC-V @ Institute of Technical Informatics/EAS Group)
- Silicon Austria Labs (tba)
- Florian Riedl and Tobias Scheipel (HaDes-V: Learning RISC-V CPU Design by Puzzling)
- Lorenz Schumm (LLVM Scheduler)
- NXP Semiconductors (NXP Engagement in RISC-V)
→ preliminary program subject to change.
If you want to contribute (talk, poster, showcase) RSVP and message separately at: tobias.scheipel@tugraz.at
RSVP now to be a part of this innovative and inclusive tech movement!
