RISC-V Events

RISC-V Tutorial at HPCA 2015

February 8, 2015San Francisco Airport Marriott Waterfront Hotel, San Francisco, CA AboutThe RISC-V tutorial will provide an opportunity to learn about the existing RISC-V infrastructure from the RISC-V team. We will first introduce RISC-V, then go through the RISC-V software stack and the Rocket Chip SoC generator. During these talks, we will feature multiple RISC-V silicon implementations as well as FPGA designs and associated software tools. The later bootcamp sessions…

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RISC-V Tutorial at HPCA 2015

We will hold a RISC-V tutorial at HPCA 2015 on Sunday, February 8th.  The tutorial will start at *1:45pm*.The RISC-V tutorial provides an opportunity to learn about the existing RISC-V infrastructure from the RISC-V team. We will first introduce RISC-V, then go through the RISC-V software stack and the Rocket Chip SoC generator. During these talks, we will feature multiple RISC-V silicon implementations as well as FPGA designs and associated software…

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RISC-V at ESSCIRC-2014

We have presented our paper “A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W RISC-V Processor with Vector Accelerators” at the 40th European Solid-State Circuits Conference, which was held at Venice, Italy. This paper details our 45nm test chip, which has two 64-bit RISC-V Rocket scalar cores, each with a Hwacha vector accelerator attached to it. The paper and the talk will be available online shortly.

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RISC-V at HotChips-26

The RISC-V team was out in force at the HotChips-26 conference manning a sponsor booth.

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The Berkeley RISC-V team pose for a group shot at the end of the conference. From left to right: Steven Bailey, Henry Cook, Sagar Karandikar, Palmer Dabbelt, Krste Asanovic, Adam Izraelevitz, Colin Schmidt, Yunsup Lee, Andrew Waterman, Brian Zimmer, Scott Beamer, David Patterson.

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