This page is a collection of available intellectual property (IP) cores and SoCs in the RISC-V ecosystem.
Please note that the Exchange can showcase available physical hardware on the Available Boards page.
| Name | Supplier | Links | Capability | Priv. spec | User spec | Primary Language | License |
|---|---|---|---|---|---|---|---|
| RV32EC_P2 | IQonIC Works | Website | RV32 | 1.11 | RV32E[M]C/RV32I[M]C | SystemVerilog | IQonIC Works Commercial License |
| RV32IC_P5 | IQonIC Works | Website | RV32 | 1.11 | RV32I[M][N][A]C | SystemVerilog | IQonIC Works Commercial License |
| RV32EC_FMP5 | IQonIC Works | Website | RV32 | Custom | RV32EC | SystemVerilog | IQonIC Works Commercial License |
| rocket | SiFive, UCB Bar | GitHub | RV32 | 1.11-draft | 2.3-draft | Chisel | BSD |
| freedom | SiFive | GitHub | RV32,RV64 | 1.11-draft | 2.3-draft | Chisel | BSD |
| Berkeley Out-of-Order Machine (BOOM) | UCB BAR | Website,GitHub | RV64 | 1.11-draft | 2.3-draft | Chisel | BSD |
| CV32E40P | OpenHW Group | GitHub | RV32 | 1.11 | RV32IM[F]C | SystemVerilog | Solderpad Hardware License v. 0.51 |
| Ibex (formerly Zero-riscy) | lowRISC | GitHub | RV32 | 1.11 | RV32I[M]C/RV32E[M]C | SystemVerilog | Apache 2.0 |
| CVA6 | OpenHW Group | GitHub | RV32,RV64 | 1.11 | RV[32/64]GC | SystemVerilog | Solderpad Hardware License v. 0.51 |
| Riscy Processors | MIT CSAIL CSG | Website,GitHub | RV32,RV64 | Bluespec | MIT | ||
| RiscyOO | MIT CSAIL CSG | GitHub | RV64 | 1.10 | RV64IMAFD | Bluespec | MIT |
| Lizard | Cornell CSL BRG | GitHub | RV64 | RV64IM | PyMTL | BSD | |
| Minerva | LambdaConcept | GitHub | RV32 | 1.10 | RV32I | nMigen | BSD |
| OPenV/mriscv | OnChipUIS | GitHub | RV32 | RV32I(?) | Verilog | MIT | |
| VexRiscv | SpinalHDL | GitHub | RV32 | 1.10 | RV32I/E[M][A][F[D]][C] | SpinalHDL | MIT |
| VexRiscv Plugins for B and K | Romain Dolbeau | GitHub | RV32 | N/A | RV32[B][K] for the VexRiscV core | SpinalHDL | MIT |
| Roa Logic RV12 | Roa Logic | GitHub | RV32 | 1.9.1 | 2.1 | SystemVerilog | Non-Commercial License |
| SCR1 | Syntacore | GitHub | RV32 | 1.10 | 2.2, RV32I/E[MC] | SystemVerilog | SHL v. 2.0 |
| SCR3 | Syntacore | Website | RV32,RV64 | 1.10 | RV[32/64]IMC[A], 2.2, milticore | SystemVerilog | commercial |
| SCR4 | Syntacore | Website | RV32,RV64 | 1.10 | RV[32/64]IMCF[DA], 2.2, milticore | SystemVerilog | commercial |
| SCR5 | Syntacore | Website | RV32,RV64 | 1.10 | RV[32/64]IMC[FDA], 2.2, milticore | SystemVerilog | commercial |
| SCR7 | Syntacore | Website | RV64 | 1.10 | RV64GC, 2.2, milticore | SystemVerilog | commercial |
| Hummingbird E200 | Bob Hu | GitHub | RV32 | 1.10 | 2.2, RV32IMAC | Verilog | Apache 2.0 |
| Shakti | IIT Madras | Website,GitLab | RV64 | 1.11 | 2.2, RV64IMAFDC | Bluespec | BSD |
| ReonV | Lucas Castro | GitHub | RV32 | VHDL | GPL v3 | ||
| PicoRV32 | Clifford Wolf | GitHub | RV32 | RV32I/E[MC] | Verilog | ISC | |
| MR1 | Tom Verbeure | GitHub | RV32 | RV32I | SpinalHDL | Unlicense | |
| SERV | Olof Kindgren | GitHub | RV32 | RV32I | Verilog | ISC | |
| SweRV EH1 | Western Digital Corporation | GitHub | RV32 | 1.11 | 2.1, RV32IMC | SystemVerilog | Apache 2.0 |
| SweRV EL2 | Western Digital Corporation | GitHub | RV32 | 1.11 | 2.1, RV32IMC | SystemVerilog | Apache 2.0 |
| SweRV EH2 | Western Digital Corporation | GitHub | RV32 | 1.11 | 2.1, RV32IMAC | SystemVerilog | Apache 2.0 |
| biRISC-V | UltraEmbedded | GitHub | RV32 | 1.11 | RV32I[M] | Verilog | Apache 2.0 |
| Reve-R | Gavin Stark | GitHub | RV32 | 1.10 | RV32IMAC | CDL | Apache 2.0 |
| L10 | Codasip | Website | RV32 | 1.0 | RV32EMC | Verilog | Codasip EULA |
| L30 | Codasip | Website | RV32 | 1.0 | RV32IMC | Verilog | Codasip EULA |
| L30F | Codasip | Website | RV32 | 1.0 | RV32IMFC | Verilog | Codasip EULA |
| L50 | Codasip | Website | RV32 | 1.0 | RV32IMC | Verilog | Codasip EULA |
| L50F | Codasip | Website | RV32 | 1.0 | RV32IMFC | Verilog | Codasip EULA |
| H50X | Codasip | Website | RV64 | 1.0 | RV64IMC | Verilog | Codasip EULA |
| H50XF | Codasip | Website | RV64 | 1.0 | RV64IMFDC | Verilog | Codasip EULA |
| A70X | Codasip | Website | RV64 | 1.0 | RV64IMAFDC | Verilog | Codasip EULA |
| DarkRISCV | Darklife | GitHub | RV32 | most of RV32I | Verilog | BSD | |
| RPU | Domipheus Labs | GitHub | RV32 | RV32I | VHDL | Apache 2.0 | |
| RV01 | Stefano Tonello | OpenCores | RV32 | 1.7 | 2.1, RV32IM | VHDL | LPGL |
| N22 | Andes | Website | RV32 | 1.11 | RV32IMAC/EMAC + Andes V5/V5e ext. | Verilog | Andes FreeStart IPEA |
| N25F | Andes | Website | RV32 | 1.11 | RV32GC + Andes V5 ext. | Verilog | Andes Commercial License |
| D25F | Andes | Website | RV32 | 1.11 | RV32GCP + Andes V5 ext. | Verilog | Andes Commercial License |
| A25 | Andes | Website | RV32 | 1.11 | RV32GCP + Sv32 + Andes V5 ext. | Verilog | Andes Commercial License |
| A25MP | Andes | Website | RV32 | 1.11 | RV32GCP + Sv32 + Andes V5 ext. + Multi-core | Verilog | Andes Commercial License |
| NX25F | Andes | Website | RV64 | 1.11 | RV64GC + Andes V5 ext. | Verilog | Andes Commercial License |
| AX25 | Andes | Website | RV64 | 1.11 | RV64GCP + Sv39/48 + Andes V5 ext. | Verilog | Andes Commercial License |
| AX25MP | Andes | Website | RV64 | 1.11 | RV64GCP + Sv39/48 + Andes V5 ext. + Multi-core | Verilog | Andes Commercial License |
| A27 | Andes | Website | RV32 | 1.11 | RV32GCP + Sv32 + Andes V5 ext. | Verilog | Andes Commercial License |
| A27L2 | Andes | Website | RV32 | 1.11 | RV32GCP + Sv39/48 + Andes V5 ext. | Verilog | Andes Commercial License |
| AX27 | Andes | Website | RV64 | 1.11 | RV64GCP + Sv39/48 + Andes V5 ext. | Verilog | Andes Commercial License |
| AX27L2 | Andes | Website | RV64 | 1.11 | RV64GCP + Sv39/48 + Andes V5 ext. | Verilog | Andes Commercial License |
| NX27V | Andes | Website | RV64 | 1.11 | RV64GCPV | Verilog | Andes Commercial License |
| N45 | Andes | Website | RV32 | 1.11 | RV32GC + Andes V5 ext. | Verilog | Andes Commercial License |
| D45 | Andes | Website | RV32 | 1.11 | RV32GCP + Andes V5 ext. | Verilog | Andes Commercial License |
| NX45 | Andes | Website | RV64 | 1.11 | RV64GC + Andes V5 ext. | Verilog | Andes Commercial License |
| A45 | Andes | Website | RV32 | 1.11 | RV32GCP + Sv32 + Andes V5 ext. | Verilog | Andes Commercial License |
| AX45 | Andes | Website | RV64 | 1.11 | RV64GCP + Sv39/48 + Andes V5 ext. | Verilog | Andes Commercial License |
| Instant SoC | FPGA Cores | Website | RV32 | RV32IM | VHDL | Free Non Commercial | |
| Taiga | Reconfigurable Computing Lab, Simon Fraser University | GitLab | RV32 | RV32IMA | SystemVerilog | Apache 2.0 | |
| Maestro | João Chrisóstomo | GitHub | RV32 | RV32I | VHDL | MIT | |
| XuanTie C910 | T-Head (Alibaba group) | Website | RV64 | 1.10 | RV64GCV + SV39 + ISA Extension + Memory model Extension + multi-core & multi-cluster(16 cores maximum) | Verilog | Alibaba commercial license |
| XuanTie C906 | T-Head (Alibaba group) | Website | RV64 | 1.10 | RV64IMA[FD]C[V] + SV39 + ISA Extension + Memory model Extension | Verilog | Alibaba commercial license |
| XuanTie E906 | T-Head (Alibaba group) | Website | RV32 | 1.10 | RV32IMA[F][D]C + ISA Extension | Verilog | Alibaba commercial license |
| XuanTie E902 | T-Head (Alibaba group) | Website | RV32 | 1.10 | RV32EMC/IMC/EC | Verilog | Alibaba commercial license |
| BM-310 | CloudBEAR | Website | RV32 | 1.10 | RV32IMC | SystemVerilog | CloudBEAR Commercial License |
| BI-350 | CloudBEAR | Website | RV32 | 1.10 | RV32IMAFC + multi-core | SystemVerilog | CloudBEAR Commercial License |
| BI-651 | CloudBEAR | Website | RV64 | 1.10 | RV64GC + multi-core | SystemVerilog | CloudBEAR Commercial License |
| BI-671 | CloudBEAR | Website | RV64 | 1.10 | RV64GC + multi-core | SystemVerilog | CloudBEAR Commercial License |
| SSRV | risclite | Website,GitHub | RV32 | 1.10 | RV32IMC | Verilog | Apache 2.0 |
| Tinyriscv | Blue Liang | GitHub | RV32 | 2.1, RV32I | Verilog | Apache 2.0 | |
| RSD | rsd-devel | GitHub | RV32 | RV32IM | SystemVerilog | Apache 2.0 | |
| Pluto | PQShield | Website | RV32 | 1.11 | RV32I[M][C] / RV32E[M][C] + Crypto Functions | Verilog | PQShield Commercial License |
| E2 | SiFive | Website | RV32 | 1.11 | RV32I(E)MAFC 2.2 | Verilog | SiFive commercial license |
| S2 | SiFive | Website | RV64 | 1.11 | RV64GC 2.2 | Verilog | SiFive commercial license |
| E3 | SiFive | Website | RV32 | 1.11 | RV32I(E)MAFDC 2.2 | Verilog | SiFive commercial license |
| S5 | SiFive | Website | RV64 | 1.11 | RV64GC 2.2 | Verilog | SiFive commercial license |
| U5 | SiFive | Website | RV64 | 1.11 | RV64GC 2.2 | Verilog | SiFive commercial license |
| E7 | SiFive | Website | RV32 | 1.11 | RV32I(E)MAFDC 2.2 | Verilog | SiFive commercial license |
| S7 | SiFive | Website | RV64 | 1.11 | RV64GC 2.2 | Verilog | SiFive commercial license |
| U7 | SiFive | Website | RV64 | 1.11 | RV64GC 2.2 | Verilog | SiFive commercial license |
| Kronos | Sonal Pinto | GitHub | RV32 | RV32I | SystemVerilog | Apache 2.0 | |
| N100 | Nuclei | Website | RV32 | 1.11 | RV32EC | Verilog | Nuclei commercial license |
| N200 | Nuclei | Website | RV32 | 1.11 | RV32IC(E)(M)(A) | Verilog | Nuclei commercial license |
| N300 | Nuclei | Website | RV32 | 1.11 | RV32IMAC(F)(D)(P) | Verilog | Nuclei commercial license |
| N600 | Nuclei | Website | RV32 | 1.11 | RV32IMAC(F)(D)(P) | Verilog | Nuclei commercial license |
| NX600 | Nuclei | Website | RV32 | 1.11 | RV64IMAC(F)(D)(P) | Verilog | Nuclei commercial license |
| UX600 | Nuclei | Website | RV64 | 1.11 | RV64IMAC(F)(D)(P) + MMU-SV39 | Verilog | Nuclei commercial license |
| WH32 | UC Techip | Website | RV32 | 1.10 | RV32GCX | Chisel | UC Techip Commercial License |
| WARP-V | Steve Hoover, Redwood EDA | GitHub | RV32 | RV32I[M][F] | TL-Verilog | BSD | |
| NEORV32 | Stephan Nolting | GitHub | RV32 | 1.12-draft | RV32[I/E][M][A][C][Zfinx][Zicsr][Zifencei] | VHDL | BSD |
| Steel | Rafael Calcada | GitHub | RV32 | 1.11 | RV32IZicsr | Verilog | MIT License |
| Klessydra-T13 | Digital Systems Lab at Sapienza University of Rome | GitHub | RV32 | 1.11 | RV32[I/E][M][A] + Kless-Vect | VHDL-2008 | Solderpad Hardware License v. 0.51 |
| Klessydra-T03 | Digital Systems Lab at Sapienza University of Rome | GitHub | RV32 | 1.11 | RV32I[A] | VHDL-2008 | Solderpad Hardware License v. 0.51 |
| Klessydra-T02 | Digital Systems Lab at Sapienza University of Rome | GitHub | RV32 | 1.11 | RV32I[A] | VHDL-2008 | Solderpad Hardware License v. 0.51 |
| Klessydra-F03 | Digital Systems Lab at Sapienza University of Rome | GitHub | RV32 | 1.11 | RV32I[A] | VHDL-2008 | Solderpad Hardware License v. 0.51 |
| MYTH Cores | MYTH Workshop students | GitHub | RV32 | RV32I | TL-Verilog | BSD | |
| Starsea_riscv | Starsea | GitHub | RV32 | RV32I | Verilog | Apache 2.0 | |
| VEGA | C-DAC | Website | RV32, RV64 | 1.10 | 2.2, RV[32/64]IMA[F][D][C], Multi-core | Bluespec | commercial |
| NutShell | UCAS & ICT,CAS | GitHub | RV64 | 1.11 | RV64IMAC | Chisel | Mulan Permissive Software License V2 |
| NOEL-V | Cobham Gaisler | Website | RV32,RV64 | 1.11 | RV32GC,RV64GC | VHDL | GPL, Commercial |
| Avispado | SemiDynamics | Website | RV64 | 1.10 | RV64GC, 2.2, multicore, V-ready | SystemVerilog | Commercial |
| Atrevido | SemiDynamics | Website | RV64 | 1.10 | RV64GC, 2.2, multicore, V-ready | SystemVerilog | Commercial |
| EMSA5-FS | Fraunhofer IPMS | Distribution, Website | RV32 | 1.11 | RV32I(E)[M][C][Zicsr][Zifencei] + ISO 26262 pre certification | SystemVerilog | Commercial |
| Fedar F1 | Emin FEDAR | GitHub | RV64 | RV64IM | Verilog-2005 | MIT | |
| ParaNut | Augsburg University of Applied Sciences | Website | RV32 | 1.1 | RV32IM, multicore | SystemC | BSD |
| Hornet | Yavuz Selim Tozlu | GitHub | RV32 | 1.1 | RV32IM | Verilog | MIT |
| Name | Supplier | Links | Capability | Core | License |
|---|---|---|---|---|---|
| Rocket Chip | SiFive, UCB BAR | GitHub,Simulator | RV32 | Rocket | BSD |
| LowRISC | lowRISC | GitHub | RV32 | RV32IM | BSD |
| PULPino | ETH Zurich, Università di Bologna | Website,GitHub | RV32 | RI5CY, Zero-riscy | Solderpad Hardware License v. 0.51 |
| PULPissimo | ETH Zurich, Università di Bologna | Website,GitHub | RV32 | RI5CY, Zero-riscy | Solderpad Hardware License v. 0.51 |
| Ariane SoC | ETH Zurich, Università di Bologna | Website,GitHub | RV64 | Ariane | Solderpad Hardware License v. 0.51 |
| OPENPULP | ETH Zurich, Università di Bologna | Website,GitHub | RV32 | RI5CY, Zero-riscy | Solderpad Hardware License v. 0.51 |
| HERO | ETH Zurich, Università di Bologna | Website,GitHub | RV32 | RI5CY, Zero-riscy | Solderpad Hardware License v. 0.51 |
| OpenPiton + Ariane | Princeton Parallel Group, ETH Zurich, Università di Bologna | Website,GitHub | RV64 | Ariane | Solderpad Hardware License v. 0.51, BSD |
| Briey | SpinalHDL | GitHub | RV32 | VexRiscv | MIT |
| Riscy | AleksandarKostovic | GitHub | RV64 | RV64I | MIT |
| Raven | RTimothyEdwards, mkkassem (efabless.com) | GitHub | RV32 | PicoRV32 | ISC |
| PicoSoC | Clifford Wolf | GitHub | RV32 | PicoRV32 | ISC |
| Icicle | Graham Edgecombe | GitHub | RV32 | RV32I | ISC |
| MIV RV32IMA L1 AHB | Microchip | Documentation, IDE, Development Environment | RV32 | Rocket RV32IMA | Apache 2.0 |
| MIV RV32IMA L1 AXI | Microchip | Documentation, IDE, Development Environment | RV32 | Rocket RV32IMA | Apache 2.0 |
| MIV RV32IMAF L1 AHB | Microchip | Documentation, IDE, Development Environment | RV32 | Rocket RV32IMAF | Apache 2.0 |
| MIV RV32IMC | Microchip | Documentation, IDE, Development Environment | RV32 | Submicron RV32I, RV32IC, RV32IM, RV32IMC | Apache 2.0 |
| FreeStart AE250 | Andes | Website | RV32 | N22 | Andes FreeStart: Free for Evaluation |
| Standard AE250 | Andes | Website, IDE | RV32 | N22 | Andes Commerical License |
| AE350 | Andes | Website, IDE | RV32,RV64 | N25F, D25F, A25, A25MP, NX25, AX25, AX25MP, A27, A27L2, AX27, AX27L2, N45, D45, A45, NX45, AX45 | Andes Commerical License |
| SCR1 SDK | Syntacore | GitHub | RV32 | SCR1, SCRx | SHL 2.0 |
| ESP | SLD Group, Columbia University | Website, GitHub | RV64 | Ariane | Apache 2.0 |
| Chipyard | UCB BAR | GitHub,Documentation | RV64 | Rocket, BOOM | BSD |
| PQSoC | PQShield | Website | RV32 | Pluto | PQShield Commercial License |
| KRZ | Sonal Pinto | GitHub | RV32 | Kronos | Apache 2.0 |
| IOb-SoC | IObundle | GitHub | RV32 | PicoRV32 | MIT |
| SweRVolf | CHIPS Alliance | GitHub | RV32 | SweRV EH1, SweRV EL2 | Apache 2.0 |
| Servant | Olof Kindgren | GitHub | RV32 | SERV | ISC |
| NEORV32 Processor | Stephan Nolting | GitHub | RV32 | NEORV32 | BSD |
| GRLIB | Cobham Gaisler | Website | RV32,RV64 | NOEL-V | GPL, Commercial |
| LiteX | Enjoy Digital | Website, GitHub | RV32,RV64 | BlackParrot, CV32E40P, Minerva, PicoRV32, Rocket, SERV, VexRiscv (SMP supported with VexRiscv) | BSD |
| Name | Supplier | Links | Core | ISA | OS | Devkit | Availability |
|---|---|---|---|---|---|---|---|
| FE310-G000 | SiFive | Datasheet | E31 | RV32IMAC | RTOS | HiFive1 | public since 2016Q4 |
| FE310-G002 | SiFive | Product page | E31 | RV32IMAC | RTOS | HiFive1 Rev B | announced 2019Q1, available for preorder |
| Freedom U540 | SiFive | Product page | U54 (4 cores), E51 (1 management core) | RV64GC (application cores), RV64IMAC (management core) | Linux | HiFive Unleashed development board | public since 2018Q1 |
| GAP8 | GreenWaves Technologies | Product page | PULP / 1 + 8 RI5CY | RV32IMC (+ Priviledged and custom ISA extensions) | RTOS | GAPuino development board | public since 2018Q1 |
| K210 | Kendryte | Product page, Datasheet, GitHub | K210 | RV64GC | Linux | KD233 development board, Sipeed MAIX/M1 development boards | public since 2018Q4 |
| RV32M1 | NXP | Reference Manual and Datasheet | RI5CY + Zero RI5CY + Arm Cortex M4F + Arm Cortex M0+ | RV32IMC | RTOS | VEGAboard | available for preorder as of 2018Q4 |
| RavenRV32 | efabless | Datasheet, GitHub | PicoRV32 | RV32IMAC | RTOS | RavenRV32 DevKit | Limited Quantity |
| PolarFire SoC | Microchip | Product Page, IDE with Renode platform | U54 (4 cores), E51 (management core) | RV64GC(U54), RV64IMAC(E51) | Linux | Microchip Icicle Kit, HiFive Unleashed Expansion Board | Icicle Kit ES available Q3 2020, HiFive Unleased Expansion Board – Q2 2018 |
| GD32VF103 | GigaDevice | Product listing,Datasheets | Bumblebee Core | RV32IMAC | RTOS | GD32VF103V-EVAL, Longan Nano etc. | Public since 2019Q4 |
| CH572, CH573 | WCH | Product Page | RISC-V3A | RV32IMAC | RTOS | public since 2019Q1 | |
| CH32F103 | WCH | Product Page Datasheet | RISC-V3A | RV32IMAC | RTOS | public since 2020Q2 | |
| MiG-V | Hensoldt Cyber GmbH | Product Page | CV6A | RV64IMAC | TrentOS | Limited |
We send occasional news about RISC-V technical progress, news, and events.
