RV32EC_P2 | IQonIC Works | Website | RV32 | 1.11 | RV32E[M]C/RV32I[M]C | SystemVerilog | IQonIC Works Commercial License |
RV32IC_P5 | IQonIC Works | Website | RV32 | 1.11 | RV32I[M][N][A]C | SystemVerilog | IQonIC Works Commercial License |
RV32EC_FMP5 | IQonIC Works | Website | RV32 | Custom | RV32EC | SystemVerilog | IQonIC Works Commercial License |
rocket | SiFive, UCB Bar | GitHub | RV32 | 1.11-draft | 2.3-draft | Chisel | BSD |
freedom | SiFive | GitHub | RV32,RV64 | 1.11-draft | 2.3-draft | Chisel | BSD |
Berkeley Out-of-Order Machine (BOOM) | UCB BAR | Website,GitHub | RV64 | 1.11-draft | 2.3-draft | Chisel | BSD |
CV32E40P | OpenHW Group | GitHub | RV32 | 1.11 | RV32IM[F]C | SystemVerilog | Solderpad Hardware License v. 0.51 |
Ibex (formerly Zero-riscy) | lowRISC | GitHub | RV32 | 1.11 | RV32I[M]C/RV32E[M]C | SystemVerilog | Apache 2.0 |
CVA6 | OpenHW Group | GitHub | RV32,RV64 | 1.11 | RV[32/64]GC | SystemVerilog | Solderpad Hardware License v. 0.51 |
Riscy Processors | MIT CSAIL CSG | Website,GitHub | RV32,RV64 | | | Bluespec | MIT |
RiscyOO | MIT CSAIL CSG | GitHub | RV64 | 1.10 | RV64IMAFD | Bluespec | MIT |
Lizard | Cornell CSL BRG | GitHub | RV64 | | RV64IM | PyMTL | BSD |
Minerva | LambdaConcept | GitHub | RV32 | 1.10 | RV32I | nMigen | BSD |
OPenV/mriscv | OnChipUIS | GitHub | RV32 | | RV32I(?) | Verilog | MIT |
VexRiscv | SpinalHDL | GitHub | RV32 | | RV32I[M][C] | SpinalHDL | MIT |
Roa Logic RV12 | Roa Logic | GitHub | RV32 | 1.9.1 | 2.1 | SystemVerilog | Non-Commercial License |
SCR1 | Syntacore | GitHub | RV32 | 1.10 | 2.2, RV32I/E[MC] | SystemVerilog | SHL v. 2.0 |
SCR3 | Syntacore | Website | RV32,RV64 | 1.10 | RV[32/64]IMC[A], 2.2, milticore | SystemVerilog | commercial |
SCR4 | Syntacore | Website | RV32,RV64 | 1.10 | RV[32/64]IMCF[DA], 2.2, milticore | SystemVerilog | commercial |
SCR5 | Syntacore | Website | RV32,RV64 | 1.10 | RV[32/64]IMC[FDA], 2.2, milticore | SystemVerilog | commercial |
SCR7 | Syntacore | Website | RV64 | 1.10 | RV64GC, 2.2, milticore | SystemVerilog | commercial |
Hummingbird E200 | Bob Hu | GitHub | RV32 | 1.10 | 2.2, RV32IMAC | Verilog | Apache 2.0 |
Shakti | IIT Madras | Website,GitLab | RV64 | 1.11 | 2.2, RV64IMAFDC | Bluespec | BSD |
ReonV | Lucas Castro | GitHub | RV32 | | | VHDL | GPL v3 |
PicoRV32 | Clifford Wolf | GitHub | RV32 | | RV32I/E[MC] | Verilog | ISC |
MR1 | Tom Verbeure | GitHub | RV32 | | RV32I | SpinalHDL | Unlicense |
SERV | Olof Kindgren | GitHub | RV32 | | RV32I | Verilog | ISC |
SweRV EH1 | Western Digital Corporation | GitHub | RV32 | 1.11 | 2.1, RV32IMC | SystemVerilog | Apache 2.0 |
SweRV EL2 | Western Digital Corporation | GitHub | RV32 | 1.11 | 2.1, RV32IMC | SystemVerilog | Apache 2.0 |
SweRV EH2 | Western Digital Corporation | GitHub | RV32 | 1.11 | 2.1, RV32IMAC | SystemVerilog | Apache 2.0 |
biRISC-V | UltraEmbedded | GitHub | RV32 | 1.11 | RV32I[M] | Verilog | Apache 2.0 |
Reve-R | Gavin Stark | GitHub | RV32 | 1.10 | RV32IMAC | CDL | Apache 2.0 |
L10 | Codasip | Website | RV32 | 1.0 | RV32EMC | Verilog | Codasip EULA |
L30 | Codasip | Website | RV32 | 1.0 | RV32IMC | Verilog | Codasip EULA |
L30F | Codasip | Website | RV32 | 1.0 | RV32IMFC | Verilog | Codasip EULA |
L50 | Codasip | Website | RV32 | 1.0 | RV32IMC | Verilog | Codasip EULA |
L50F | Codasip | Website | RV32 | 1.0 | RV32IMFC | Verilog | Codasip EULA |
H50X | Codasip | Website | RV64 | 1.0 | RV64IMC | Verilog | Codasip EULA |
H50XF | Codasip | Website | RV64 | 1.0 | RV64IMFDC | Verilog | Codasip EULA |
A70X | Codasip | Website | RV64 | 1.0 | RV64IMAFDC | Verilog | Codasip EULA |
DarkRISCV | Darklife | GitHub | RV32 | | most of RV32I | Verilog | BSD |
RPU | Domipheus Labs | GitHub | RV32 | | RV32I | VHDL | Apache 2.0 |
RV01 | Stefano Tonello | OpenCores | RV32 | 1.7 | 2.1, RV32IM | VHDL | LPGL |
N22 | Andes | Website | RV32 | 1.11 | RV32IMAC/EMAC + Andes V5/V5e ext. | Verilog | Andes FreeStart IPEA |
N25F | Andes | Website | RV32 | 1.11 | RV32GC + Andes V5 ext. | Verilog | Andes Commercial License |
D25F | Andes | Website | RV32 | 1.11 | RV32GCP + Andes V5 ext. | Verilog | Andes Commercial License |
A25 | Andes | Website | RV32 | 1.11 | RV32GCP + SV32 + Andes V5 ext. | Verilog | Andes Commercial License |
A25MP | Andes | Website | RV32 | 1.11 | RV32GCP + SV32 + Andes V5 ext. + Multi-core | Verilog | Andes Commercial License |
NX25F | Andes | Website | RV64 | 1.11 | RV64GC + Andes V5 ext. | Verilog | Andes Commercial License |
AX25 | Andes | Website | RV64 | 1.11 | RV64GCP + SV39/48 + Andes V5 ext. | Verilog | Andes Commercial License |
AX25MP | Andes | Website | RV64 | 1.11 | RV64GCP + SV39/48 + Andes V5 ext. + Multi-core | Verilog | Andes Commercial License |
Instant SoC | FPGA Cores | Website | RV32 | | RV32IM | VHDL | Free Non Commercial |
Taiga | Reconfigurable Computing Lab, Simon Fraser University | GitLab | RV32 | | RV32IMA | SystemVerilog | Apache 2.0 |
Maestro | João Chrisóstomo | GitHub | RV32 | | RV32I | VHDL | MIT |
XuanTie C910 | T-Head (Alibaba group) | Website | RV64 | 1.10 | RV64GCV + SV39 + ISA Extension + Memory model Extension + multi-core & multi-cluster(16 cores maximum) | Verilog | Alibaba commercial license |
XuanTie C906 | T-Head (Alibaba group) | Website | RV64 | 1.10 | RV64IMA[FD]C[V] + SV39 + ISA Extension + Memory model Extension | Verilog | Alibaba commercial license |
XuanTie E906 | T-Head (Alibaba group) | Website | RV32 | 1.10 | RV32IMA[F][D]C + ISA Extension | Verilog | Alibaba commercial license |
XuanTie E902 | T-Head (Alibaba group) | Website | RV32 | 1.10 | RV32EMC/IMC/EC | Verilog | Alibaba commercial license |
BM-310 | CloudBEAR | Website | RV32 | 1.10 | RV32IMC | SystemVerilog | CloudBEAR Commercial License |
BI-350 | CloudBEAR | Website | RV32 | 1.10 | RV32IMAFC + multi-core | SystemVerilog | CloudBEAR Commercial License |
BI-651 | CloudBEAR | Website | RV64 | 1.10 | RV64GC + multi-core | SystemVerilog | CloudBEAR Commercial License |
BI-671 | CloudBEAR | Website | RV64 | 1.10 | RV64GC + multi-core | SystemVerilog | CloudBEAR Commercial License |
SSRV | risclite | Website,GitHub | RV32 | 1.10 | RV32IMC | Verilog | Apache 2.0 |
Tinyriscv | Blue Liang | GitHub | RV32 | | 2.1, RV32I | Verilog | Apache 2.0 |
RSD | rsd-devel | GitHub | RV32 | | RV32IM | SystemVerilog | Apache 2.0 |
Pluto | PQShield | Website | RV32 | 1.11 | RV32I[M][C] / RV32E[M][C] + Crypto Functions | Verilog | PQShield Commercial License |
E2 | SiFive | Website | RV32 | 1.11 | RV32I(E)MAFC 2.2 | Verilog | SiFive commercial license |
S2 | SiFive | Website | RV64 | 1.11 | RV64GC 2.2 | Verilog | SiFive commercial license |
E3 | SiFive | Website | RV32 | 1.11 | RV32I(E)MAFDC 2.2 | Verilog | SiFive commercial license |
S5 | SiFive | Website | RV64 | 1.11 | RV64GC 2.2 | Verilog | SiFive commercial license |
U5 | SiFive | Website | RV64 | 1.11 | RV64GC 2.2 | Verilog | SiFive commercial license |
E7 | SiFive | Website | RV32 | 1.11 | RV32I(E)MAFDC 2.2 | Verilog | SiFive commercial license |
S7 | SiFive | Website | RV64 | 1.11 | RV64GC 2.2 | Verilog | SiFive commercial license |
U7 | SiFive | Website | RV64 | 1.11 | RV64GC 2.2 | Verilog | SiFive commercial license |
Kronos | Sonal Pinto | GitHub | RV32 | | RV32I | SystemVerilog | Apache 2.0 |
N100 | Nuclei | Website | RV32 | 1.11 | RV32EC | Verilog | Nuclei commercial license |
N200 | Nuclei | Website | RV32 | 1.11 | RV32IC(E)(M)(A) | Verilog | Nuclei commercial license |
N300 | Nuclei | Website | RV32 | 1.11 | RV32IMAC(F)(D)(P) | Verilog | Nuclei commercial license |
N600 | Nuclei | Website | RV32 | 1.11 | RV32IMAC(F)(D)(P) | Verilog | Nuclei commercial license |
NX600 | Nuclei | Website | RV32 | 1.11 | RV64IMAC(F)(D)(P) | Verilog | Nuclei commercial license |
UX600 | Nuclei | Website | RV64 | 1.11 | RV64IMAC(F)(D)(P) + MMU-SV39 | Verilog | Nuclei commercial license |
WH32 | UC Techip | Website | RV32 | 1.10 | RV32GCX | Chisel | UC Techip Commercial License |
WARP-V | Steve Hoover, Redwood EDA | GitHub | RV32 | | RV32I[M][F] | TL-Verilog | BSD |
NEORV32 | Stephan Nolting | GitHub | RV32 | 1.12-draft | 2.2, RV32[I/E][M][A][C][Zicsr][Zifencei] | VHDL | BSD |
Steel | Rafael Calcada | GitHub | RV32 | 1.11 | RV32IZicsr | Verilog | MIT License |
Klessydra-T13 | Digital Systems Lab at Sapienza University of Rome | GitHub | RV32 | 1.11 | RV32[I/E][M][A] + Kless-Vect | VHDL-2008 | Solderpad Hardware License v. 0.51 |
Klessydra-T03 | Digital Systems Lab at Sapienza University of Rome | GitHub | RV32 | 1.11 | RV32I[A] | VHDL-2008 | Solderpad Hardware License v. 0.51 |
Klessydra-T02 | Digital Systems Lab at Sapienza University of Rome | GitHub | RV32 | 1.11 | RV32I[A] | VHDL-2008 | Solderpad Hardware License v. 0.51 |
Klessydra-F03 | Digital Systems Lab at Sapienza University of Rome | GitHub | RV32 | 1.11 | RV32I[A] | VHDL-2008 | Solderpad Hardware License v. 0.51 |
MYTH Cores | MYTH Workshop students | GitHub | RV32 | | RV32I | TL-Verilog | BSD |
Starsea_riscv | Starsea | GitHub | RV32 | | RV32I | Verilog | Apache 2.0 |
VEGA | C-DAC | Website | RV32, RV64 | 1.10 | 2.2, RV[32/64]IMA[F][D][C], Multi-core | Bluespec | commercial |
NutShell | UCAS & ICT,CAS | GitHub | RV64 | 1.11 | RV64IMAC | Chisel | Mulan Permissive Software License V2 |
NOEL-V | Cobham Gaisler | Website | RV32,RV64 | 1.11 | RV32GC,RV64GC | VHDL | GPL, Commercial |