The RISC-V instruction set architecture (ISA) and related specifications are developed, ratified and maintained by contributing members and technical working groups.
RISC-V Everywhere
RISC-V International is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community.
About UsThere are many ways to get involved with RISC-V
Developers
For organizations and individuals interested in contributing as a developer, learn more about RISC-V training programs, working groups, and our ambassador and advocacy programs.
Membership
RISC-V International is changing the way the industry works together and collaborates. Learn more about supporting the industry’s future de facto ISA for design innovation.
Meet us at an upcoming event
This October, the global RISC-V community – including technical, industry, domain, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara, California to share technology breakthroughs, industry milestones, and case studies, as well as to network and build relationships. Come be part of the RISC-V movement.
Get certified in RISC-V
RISC-V Fundamentals (LFD210) + RISC-V Foundational Associate (RVFA) Exam Bundle
This course is designed for computer engineers and programmers looking to acquire the knowledge and skills necessary to work with RISC-V processors and software, giving you a competitive edge in the job market. This course is an essential learning experience for anyone looking to enhance their career in the tech industry.
Latest from RISC-V
Learning Computer Architecture with a Visual Simulation of RISC-V Processors
Project Snapshot This work presents an interactive way of teaching computer architecture using Logisim Evolution, enabling students to construct and debug single-cycle and pipelined CPUs. Enhancements to Logisim Evolution allow dynamic editing of components, reinforcing theoretical concepts with hands-on experience. The proposed lab assignments progressively guide students through key processor…
Full-Fat, Kernel-Ready: Why RISC-V Linux Needs Everyone Upstream
For hardware makers, the cost of skipping the upstream has never been higher. I talk to the Linux leaders working to ensure code hits the kernel before silicon hits shelves.
RISC-V Summit China 2025: Reflections from a RISC-V Software Contributor
By Guodong Xu, Director China Operations, RISCstar Solutions The 2025 RISC-V Summit China reached an unprecedented level of excitement, drawing a record-breaking crowd of over 4,000 attendees. The main venue was filled to capacity, with many standing along the walls just to be part of the event. This was my…