The RISC-V instruction set architecture (ISA) and related specifications are developed, ratified and maintained by contributing members and technical working groups.
RISC-V Everywhere
RISC-V International is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community.
About UsThere are many ways to get involved with RISC-V
Developers
For organizations and individuals interested in contributing as a developer, learn more about RISC-V training programs, working groups, and our ambassador and advocacy programs.
Membership
RISC-V International is changing the way the industry works together and collaborates. Learn more about supporting the industry’s future de facto ISA for design innovation.
Meet us at an upcoming event
This October, the global RISC-V community – including technical, industry, domain, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara, California to share technology breakthroughs, industry milestones, and case studies, as well as to network and build relationships. Come be part of the RISC-V movement.
Get certified in RISC-V
RISC-V Fundamentals (LFD210) + RISC-V Foundational Associate (RVFA) Exam Bundle
This course is designed for computer engineers and programmers looking to acquire the knowledge and skills necessary to work with RISC-V processors and software, giving you a competitive edge in the job market. This course is an essential learning experience for anyone looking to enhance their career in the tech industry.
Latest from RISC-V
TYRCA: A RISC-V Tightly-Coupled Accelerator For Code-Based Cryptography
Project Snapshot Post-quantum cryptography (PQC) has garnered significant attention across various communities, particularly with the National Institute of Standards and Technology (NIST) advancing to the fourth round of PQC standardization. One of the leading candidates is Hamming Quasi-Cyclic (HQC), which received a significant update on February 23, 2024. This update,…
HaDes-V – Learning by Puzzling: A Modular Approach to RISC-V Processor Design Education
Project Snapshot HaDes-V is an Open Educational Resource for learning microcontroller design. It guides through creating a 5-stage pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed and taught at Graz University of Technology, this resource combines hands-on exercises in hardware/software co-design with practical processor implementation on FPGAs. In…
RISE RISC-V Developer Appreciation Program
Get paid to contribute to the RISC-V ecosystem