Remote – preferred candidate to be located in either Portland or Vancouver
As a founding premier member of RISC-V International, Andes is the leading supplier and technological innovator in the RISC-V market with a wide range of processor products fulfilling performance/area/power requirements. Andes has perfected the technology of quick and efficient design of custom extensions to its proprietary CPU. With over 10 billion cumulative shipments of SoCs embedded with Andes CPU IP, Andes products have covered audio, Bluetooth, gaming, GPS, machine learning, MCU and more. Our design innovation enables us to quickly adapt to the rapidly evolving demands of RISC-V customers.
Founded in 2005, Andes yearly revenue has tripled in size from $10 million in 2017 to $30 million in 2021. Andes was ranked among “100 Fastest-Growing Companies” in 2020 by CommonWealth Magazine. Headquartered in Taiwan, Andes is capitalizing on its current growth by branching out its offices to the US and Canada to expand on its current 300 employee workforce. Employees are valued as the key ingredient to the success of the company. They will have an opportunity to create a strong and positive impact on the company, where feedback is encouraged and implemented.
This role is a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will get the opportunity to work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.
As a member of this team, you will help guide verification methodologies, analyze problems and devise best QoR solutions. You will be able to participate in engineering discussions and drive analysis and propose directions. We value diligence, detail orientation and a penchant for creating high-quality results efficiently. Ideal applicants will have a passion for technical advances, CPU architecture and have a keen interest in tackling present day verification problems.
Daily Activities includes:
- Communication with peers to discuss technical details
- Competitive analysis and critique pros and cons, such as the balance of performance, area, power
- Explicit CPU hardware design ranging such as fetch units, scheduling, complex vector or floating-point maths, load-store units, coherent memory access or multi-core debug architecture
- Design quality analysis including synthesis to assess frequency, area, power quality
- Providing technical guidance to junior members of the team
- Technical documentation
- Over 3 years for Mid level/10 years for Senior level of applicable work experience
- Bachelor’s or Master’s degree in related engineering field
- Strong communication skills
- Experience in bus protocols such as AXI, CHI
- Experience of ASIC design techniques, pipelines and basic CPU microarchitecture
- Experience in synthesis, physical layout concepts, static timing analysis, clock domain crossing
- Strong mastery using Verilog, System Verilog
- Strong mastery using Unix and scripting languages such as make, shell, perl or python
Additional Technical Requirements for Senior Level:
- Experience of advanced CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug) and assembly languages
- Patience and good leadership skills
- Strong desire to learn and willing to devote extra effort to achieve perfection
- Strong team player and possess a positive attitude
- Experience or knowledge in verification techniques such as UVM, formal, coverage analysis, bug tracking
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