The RISC-V ISA specifications, extensions, and supporting documents are collaboratively developed, ratified, and maintained by contributing members of RISC-V International.
These specifications are all free and publicly available.
Ratified Specification
The RISC-V open-standard instruction set architecture (ISA) defines the fundamental guidelines for designing and implementing RISC-V processors.
VIEW RATIFIED SPECSSPECS UNDER DEVELOPMENTView Original Specifications »
Andrew Waterman, Yunsup Lee, David A. Patterson, and Krste Asanović, “The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA”
Technical Report UCB/EECS-2011-62, EECS Department, University of California, Berkeley, May 13, 2011
Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanović, “The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.0”,
Technical Report UCB/EECS-2014-54, EECS Department, University of California, Berkeley, May 7, 2014
Andrew Waterman, Yunsup Lee, Rimas Avižienis, David A. Patterson, and Krste Asanović, “The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.7”
Technical Report UCB/EECS-2015-49, EECS Department, University of California, Berkeley, May 9, 2015.
Andrew Waterman, Yunsup Lee, David A. Patterson, and Krste Asanović, “The RISC-V Compressed Instruction Set Manual, Version 1.7”
Technical Report UCB/EECS-2015-157, EECS Department, University of California, Berkeley, May 28, 2015.
Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanović, “The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.1”,
Technical Report UCB/EECS-2016-118, EECS Department, University of California, Berkeley, May 31, 2016.
Andrew Waterman, Yunsup Lee, Rimas Avižienis, David A. Patterson, and Krste Asanović, “The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.9”,
Technical Report UCB/EECS-2016-129, EECS Department, University of California, Berkeley, July 8, 2016